From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0061C433E0 for ; Fri, 5 Mar 2021 07:53:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 73FFE64FCF for ; Fri, 5 Mar 2021 07:53:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229505AbhCEHxk (ORCPT ); Fri, 5 Mar 2021 02:53:40 -0500 Received: from muru.com ([72.249.23.125]:39712 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229458AbhCEHxj (ORCPT ); Fri, 5 Mar 2021 02:53:39 -0500 Received: from atomide.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id 701C380BA; Fri, 5 Mar 2021 07:54:17 +0000 (UTC) Date: Fri, 5 Mar 2021 09:53:35 +0200 From: Tony Lindgren To: Grygorii Strashko Cc: Daniel Lezcano , Thomas Gleixner , Keerthy , linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 1/3] clocksource/drivers/timer-ti-dm: Fix posted mode status check order Message-ID: References: <20210304072135.52712-1-tony@atomide.com> <20210304072135.52712-2-tony@atomide.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Grygorii Strashko [210304 20:58]: > On 04/03/2021 09:21, Tony Lindgren wrote: > > When the timer is configured in posted mode, we need to check the write- > > posted status register (TWPS) before writing to the register. ... > > --- a/drivers/clocksource/timer-ti-dm-systimer.c > > +++ b/drivers/clocksource/timer-ti-dm-systimer.c > > @@ -449,13 +449,13 @@ static int dmtimer_set_next_event(unsigned long cycles, > > struct dmtimer_systimer *t = &clkevt->t; > > void __iomem *pend = t->base + t->pend; > > - writel_relaxed(0xffffffff - cycles, t->base + t->counter); > > while (readl_relaxed(pend) & WP_TCRR) > > cpu_relax(); > > + writel_relaxed(0xffffffff - cycles, t->base + t->counter); > > - writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl); > > while (readl_relaxed(pend) & WP_TCLR) > > cpu_relax(); > > + writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl); > > It seems static [and inline] helper here could be better solution. no? Well we wanted to get rid of the confusing macros. And in this case I suspect we can eventually do just one read of the pending register for the registers used mask rather than check the status separately multiple times. But that needs to be carefully tested and is not a fix :) Regards, Tony