From: Peter Zijlstra <peterz@infradead.org>
To: kan.liang@linux.intel.com
Cc: mingo@kernel.org, linux-kernel@vger.kernel.org, acme@kernel.org,
tglx@linutronix.de, bp@alien8.de, namhyung@kernel.org,
jolsa@redhat.com, ak@linux.intel.com, yao.jin@linux.intel.com,
alexander.shishkin@linux.intel.com, adrian.hunter@intel.com,
Mark Rutland <mark.rutland@arm.com>
Subject: Re: [PATCH V2 20/25] perf/x86/intel: Add Alder Lake Hybrid support
Date: Thu, 11 Mar 2021 17:09:25 +0100 [thread overview]
Message-ID: <YEpAtTttSxMVDWYp@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <1615394281-68214-21-git-send-email-kan.liang@linux.intel.com>
On Wed, Mar 10, 2021 at 08:37:56AM -0800, kan.liang@linux.intel.com wrote:
> From: Kan Liang <kan.liang@linux.intel.com>
>
> Alder Lake Hybrid system has two different types of core, Golden Cove
> core and Gracemont core. The Golden Cove core is registered to
> "cpu_core" PMU. The Gracemont core is registered to "cpu_atom" PMU.
>
> The difference between the two PMUs include:
> - Number of GP and fixed counters
> - Events
> - The "cpu_core" PMU supports Topdown metrics.
> The "cpu_atom" PMU supports PEBS-via-PT.
>
> The "cpu_core" PMU is similar to the Sapphire Rapids PMU, but without
> PMEM.
> The "cpu_atom" PMU is similar to Tremont, but with different
> event_constraints, extra_regs and number of counters.
>
> + /* Initialize big core specific PerfMon capabilities.*/
> + pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
> + pmu->name = "cpu_core";
> + /* Initialize Atom core specific PerfMon capabilities.*/
> + pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
> + pmu->name = "cpu_atom";
So do these things use the same event lists as SPR and TNT? Is there any
way to discover that, because AFAICT /proc/cpuinfo will say every CPU
is 'Alderlake', and the above also doesn't give any clue.
FWIW, ARM big.LITTLE does discriminate in its /proc/cpuinfo, but I'm not
entirely sure it's really useful. Mark said perf userspace uses
somethink akin to our CPUID, except exposed through sysfs, to find the
event lists.
My desktop has: cpu/caps/pmu_name and that gives "skylake", do we want
the above to have cpu_core/caps/pmu_name give "sapphire_rapids" etc.. ?
next prev parent reply other threads:[~2021-03-11 16:10 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-10 16:37 [PATCH V2 00/25] Add Alder Lake support for perf (kernel) kan.liang
2021-03-10 16:37 ` [PATCH V2 1/25] x86/cpufeatures: Enumerate Intel Hybrid Technology feature bit kan.liang
2021-03-10 16:53 ` Borislav Petkov
2021-03-10 19:33 ` Srinivas Pandruvada
2021-03-10 19:46 ` Ricardo Neri
2021-03-10 20:01 ` Borislav Petkov
2021-03-10 22:25 ` Ricardo Neri
2021-03-10 22:32 ` Liang, Kan
2021-03-10 22:42 ` Srinivas Pandruvada
2021-03-10 16:37 ` [PATCH V2 2/25] x86/cpu: Add helper functions to get parameters of hybrid CPUs kan.liang
2021-03-11 11:48 ` Borislav Petkov
2021-03-10 16:37 ` [PATCH V2 03/25] perf/x86: Track pmu in per-CPU cpu_hw_events kan.liang
2021-03-10 16:37 ` [PATCH V2 04/25] perf/x86/intel: Hybrid PMU support for perf capabilities kan.liang
2021-03-10 16:37 ` [PATCH V2 05/25] perf/x86: Hybrid PMU support for intel_ctrl kan.liang
2021-03-10 16:37 ` [PATCH V2 06/25] perf/x86: Hybrid PMU support for counters kan.liang
2021-03-10 16:37 ` [PATCH V2 07/25] perf/x86: Hybrid PMU support for unconstrained kan.liang
2021-03-10 16:37 ` [PATCH V2 08/25] perf/x86: Hybrid PMU support for hardware cache event kan.liang
2021-03-11 11:07 ` Peter Zijlstra
2021-03-11 15:09 ` Liang, Kan
2021-03-10 16:37 ` [PATCH V2 09/25] perf/x86: Hybrid PMU support for event constraints kan.liang
2021-03-10 16:37 ` [PATCH V2 10/25] perf/x86: Hybrid PMU support for extra_regs kan.liang
2021-03-10 16:37 ` [PATCH V2 11/25] perf/x86/intel: Factor out intel_pmu_check_num_counters kan.liang
2021-03-10 16:37 ` [PATCH V2 12/25] perf/x86/intel: Factor out intel_pmu_check_event_constraints kan.liang
2021-03-10 16:37 ` [PATCH V2 13/25] perf/x86/intel: Factor out intel_pmu_check_extra_regs kan.liang
2021-03-10 16:37 ` [PATCH V2 14/25] perf/x86: Remove temporary pmu assignment in event_init kan.liang
2021-03-10 16:37 ` [PATCH V2 15/25] perf/x86: Factor out x86_pmu_show_pmu_cap kan.liang
2021-03-10 16:37 ` [PATCH V2 16/25] perf/x86: Register hybrid PMUs kan.liang
2021-03-10 16:50 ` Dave Hansen
2021-03-10 17:38 ` Liang, Kan
2021-03-11 11:56 ` Peter Zijlstra
2021-03-11 12:17 ` Peter Zijlstra
2021-03-11 12:30 ` Peter Zijlstra
2021-03-11 12:19 ` Peter Zijlstra
2021-03-11 12:34 ` Peter Zijlstra
2021-03-11 15:41 ` Liang, Kan
2021-03-11 16:13 ` Peter Zijlstra
2021-03-11 17:53 ` Andi Kleen
2021-03-11 19:54 ` Peter Zijlstra
2021-03-10 16:37 ` [PATCH V2 17/25] perf/x86: Add structures for the attributes of Hybrid PMUs kan.liang
2021-03-10 16:37 ` [PATCH V2 18/25] perf/x86/intel: Add attr_update for " kan.liang
2021-03-10 16:37 ` [PATCH V2 19/25] perf/x86: Support filter_match callback kan.liang
2021-03-10 16:37 ` [PATCH V2 20/25] perf/x86/intel: Add Alder Lake Hybrid support kan.liang
2021-03-11 12:51 ` Peter Zijlstra
2021-03-11 16:09 ` Peter Zijlstra [this message]
2021-03-11 16:32 ` Peter Zijlstra
2021-03-11 17:31 ` Liang, Kan
2021-03-11 16:53 ` Liang, Kan
2021-03-11 17:25 ` Liang, Kan
2021-03-11 19:58 ` Peter Zijlstra
2021-03-11 20:30 ` Andi Kleen
2021-03-11 20:37 ` Peter Zijlstra
2021-03-11 20:32 ` Liang, Kan
2021-03-11 20:47 ` Peter Zijlstra
2021-03-11 21:09 ` Luck, Tony
2021-03-11 21:43 ` Peter Zijlstra
2021-03-12 0:00 ` Andi Kleen
2021-03-10 16:37 ` [PATCH V2 21/25] perf: Introduce PERF_TYPE_HARDWARE_PMU and PERF_TYPE_HW_CACHE_PMU kan.liang
2021-03-10 16:37 ` [PATCH V2 22/25] perf/x86/intel/uncore: Add Alder Lake support kan.liang
2021-03-10 16:37 ` [PATCH V2 23/25] perf/x86/msr: Add Alder Lake CPU support kan.liang
2021-03-10 16:38 ` [PATCH V2 24/25] perf/x86/cstate: " kan.liang
2021-03-10 16:38 ` [PATCH V2 25/25] perf/x86/rapl: Add support for Intel Alder Lake kan.liang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=YEpAtTttSxMVDWYp@hirez.programming.kicks-ass.net \
--to=peterz@infradead.org \
--cc=acme@kernel.org \
--cc=adrian.hunter@intel.com \
--cc=ak@linux.intel.com \
--cc=alexander.shishkin@linux.intel.com \
--cc=bp@alien8.de \
--cc=jolsa@redhat.com \
--cc=kan.liang@linux.intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=mingo@kernel.org \
--cc=namhyung@kernel.org \
--cc=tglx@linutronix.de \
--cc=yao.jin@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).