From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C58FC433E0 for ; Thu, 11 Mar 2021 16:32:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D7DC064FA7 for ; Thu, 11 Mar 2021 16:32:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229690AbhCKQbo (ORCPT ); Thu, 11 Mar 2021 11:31:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57530 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229689AbhCKQbT (ORCPT ); Thu, 11 Mar 2021 11:31:19 -0500 Received: from mail-oi1-x231.google.com (mail-oi1-x231.google.com [IPv6:2607:f8b0:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 996BFC061761 for ; Thu, 11 Mar 2021 08:31:19 -0800 (PST) Received: by mail-oi1-x231.google.com with SMTP id q130so4780722oif.13 for ; Thu, 11 Mar 2021 08:31:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=dxCOzqw4OU5tNnGsb0G/mX+YTbwJwLies3DsLPBifnM=; b=YTc1qrhxjsnX9+9VweICdIymergn23QKmhuRY3DiCjo8y5jB/7SeamD5tYP0HCTAtP VKeFHLfTynEAgFT7EF+MGGhmXdSFJmyAN+ZwfWmdeKKofBwFT7o9duX2Nkt1SRdsS3YV YpSLGHo0DxX6/hRelFakKkU5BLbiBpx+xjiV5Ae634VWo2hVBWYm1WVtSBBa1rzb4cW2 Fyylx8ycQyIsCgjCgIE7n5EWdFvV0RzoT07McHPiX9wcV50MxBDyKgmGZd0EXmLkPR/Q 8JjTZR0eccWaE3y4aA5ZCoUypcRkHuFplhfZo9TZ3E6xIqczVYyXfGohGbjdUrimmwNh 1A9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=dxCOzqw4OU5tNnGsb0G/mX+YTbwJwLies3DsLPBifnM=; b=qVK7/6aLBKiBKTXd7vdkBe0SAeP/V3/G1C2XwI23TEL5mTYy21Pgscs9jqrHotXtlE H8NrJMJLiDA/gvz2MeStcMC0u9eORBRcHRVuA/FYYaLccCXA7sOR3COdzBfWjhFMBXJw w9IJ1MSacSMsd/hL5XbdAqEDch0vHZWzDBaVD3PwLOLCEAY1lDy21uauBJrKgiwQgSYw oTqjmES7ERlb8EO5T9dIRH5MXnIJqhy8Bq5hi9npU5MdVG8Tl/Ndx171LBX2eitnrBA9 4J2e7DkbH5wTVNAVyCJRG08LwQL/vbr3z6SYUTumswKQZ9OA8L10+WcXLMo7U7Y7ZttE KXbg== X-Gm-Message-State: AOAM533Jrmla99cahOCu0D5O+Zx3XhtCv5BukyQFCiB2CtyYc0q7La/a KiFiXc/ByblehWGMltHulyua3g== X-Google-Smtp-Source: ABdhPJy8g+TsPd2NUk3K/DbblvGVMt7+KSupjIq5Fp3bjoYNBvD/mp6WLJf/7RBLg4CdHqxr5X8eCg== X-Received: by 2002:aca:c2d7:: with SMTP id s206mr6544020oif.95.1615480278918; Thu, 11 Mar 2021 08:31:18 -0800 (PST) Received: from builder.lan (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id s193sm625571oih.52.2021.03.11.08.31.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Mar 2021 08:31:18 -0800 (PST) Date: Thu, 11 Mar 2021 10:31:16 -0600 From: Bjorn Andersson To: Sai Prakash Ranjan Cc: Souradeep Chowdhury , Rob Herring , Andy Gross , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, sibis@codeaurora.org, Rajendra Nayak , vkoul@kernel.org Subject: Re: [PATCH V1 2/6] soc: qcom: dcc: Add driver support for Data Capture and Compare unit(DCC) Message-ID: References: <48556129a02c9f7cd0b31b2e8ee0f168e6d211b7.1615393454.git.schowdhu@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu 11 Mar 00:19 CST 2021, Sai Prakash Ranjan wrote: > Hi Bjorn, > > On 2021-03-11 04:49, Bjorn Andersson wrote: > > On Wed 10 Mar 10:46 CST 2021, Souradeep Chowdhury wrote: > > > > > The DCC is a DMA Engine designed to capture and store data > > > during system crash or software triggers. The DCC operates > > > based on link list entries which provides it with data and > > > addresses and the function it needs to perform. These > > > functions are read, write and loop. Added the basic driver > > > in this patch which contains a probe method which instantiates > > > the resources needed by the driver. DCC has it's own SRAM which > > > needs to be instantiated at probe time as well. > > > > > > > So to summarize, the DCC will upon a crash copy the configured region > > into the dcc-ram, where it can be retrieved either by dumping the memory > > over USB or from sysfs on the next boot? > > > > Not just the next boot, but also for the current boot via /dev/dcc_sram, > more below. > Interesting! > > > Signed-off-by: Souradeep Chowdhury > > > --- > > > drivers/soc/qcom/Kconfig | 8 + > > > drivers/soc/qcom/Makefile | 1 + > > > drivers/soc/qcom/dcc.c | 388 > > > ++++++++++++++++++++++++++++++++++++++++++++++ > > > 3 files changed, 397 insertions(+) > > > create mode 100644 drivers/soc/qcom/dcc.c > > > > > ... > > > > > How about implementing this using pstore instead of exposing it through > > a custom /dev/dcc_sram (if I read the code correclty) > > > > Using pstore is definitely a good suggestion, we have been thinking of > adding it as a separate change once the basic support for DCC gets in. > But pstore ram backend again depends on warm reboot which is present only > in chrome compute platforms but android platforms do not officially support > warm reboot. Pstore with block devices as a backend would be ideal but it > is still a work in progress to use mmc as the backend [1]. > I was under the impression that we can have multiple pstore implementations active, so we would have ramoops and dcc presented side by side after such restart. Perhaps that's a misunderstanding on my part? > Now the other reason as to why we need this dev interface in addition to > pstore, > > * Pstore contents are retrieved on the next boot, but DCC SRAM contents > can be collected via dev interface for the current boot via SW trigger. > Lets say we have some non-fatal errors in one of the subsystems and we > want to analyze the register values, it becomes as simple as configuring > that region, trigger dcc and collect the sram contents and parse it. > > echo "addr" > /sys/bus/platform/devices/***.dcc/config > echo 1 > /sys/bus/platform/devices/***.dcc/trigger > cat /dev/dcc_sram > dcc_sram.bin > python dcc_parser.py -s dcc_sram.bin --v2 -o output/ > > We don't have to reboot at all for SW triggers. This is very useful and > widely used internally. > > Is the custom /dev/dcc_sram not recommended because of the dependency on > the userspace component being not available openly? If so, we already have > the dcc parser upstream which we use to extract the sram contents [2]. > My concern is that we come up with a custom chardev implementation for something that already exists or should exist in a more generic form. In the runtime sequence above, why don't you have trigger just generate a devcoredump? But perhaps the answer is that we want a unified interface between the restart and runtime use cases? It would be nice to have some more details of how I can use this and how to operate the sysfs interface to achieve that, would you be able to elaborate on this? Regards, Bjorn > [1] > https://lore.kernel.org/lkml/20210120121047.2601-1-bbudiredla@marvell.com/ > [2] https://source.codeaurora.org/quic/la/platform/vendor/qcom-opensource/tools/tree/dcc_parser > > Thanks, > Sai > > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation