On Tue, Mar 02, 2021 at 03:24:59PM +0300, Dmitry Osipenko wrote:
> The SW-initiated power gate toggling is dropped by PMC if there is
> contention with a HW-initiated toggling, i.e. when one of CPU cores is
> gated by cpuidle driver. Software should retry the toggling after 10
> microseconds on Tegra20/30 SoCs, hence add the retrying. On Tegra114+ the
> toggling method was changed in hardware, the TOGGLE_START bit indicates
> whether PMC is busy or could accept the command to toggle, hence handle
> that bit properly.
> 
> The problem pops up after enabling dynamic power gating of 3d hardware,
> where 3d power domain fails to turn on/off "randomly".
> 
> The programming sequence and quirks are documented in TRMs, but PMC
> driver obliviously re-used the Tegra20 logic for Tegra30+, which strikes
> back now. The 10 microseconds and other timeouts aren't documented in TRM,
> they are taken from downstream kernel.
> 
> Link: https://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=commit;h=311dd1c318b70e93bcefec15456a10ff2b9eb0ff
> Link: https://nv-tegra.nvidia.com/gitweb/?p=linux-3.10.git;a=commit;h=7f36693c47cb23730a6b2822e0975be65fb0c51d
> Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
> Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124
> Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---
>  drivers/soc/tegra/pmc.c | 70 ++++++++++++++++++++++++++++++++++++++---
>  1 file changed, 65 insertions(+), 5 deletions(-)

Applied, thanks.

Thierry