From: Thierry Reding <thierry.reding@gmail.com>
To: Dmitry Osipenko <digetx@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>,
Peter Geis <pgwipeout@gmail.com>,
Matt Merhar <mattmerhar@protonmail.com>,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 3/5] soc/tegra: pmc: Ensure that clock rates aren't too high
Date: Thu, 25 Mar 2021 15:39:30 +0100 [thread overview]
Message-ID: <YFygotHKjgPQ/R4G@orome.fritz.box> (raw)
In-Reply-To: <20210302122502.20874-4-digetx@gmail.com>
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On Tue, Mar 02, 2021 at 03:25:00PM +0300, Dmitry Osipenko wrote:
> Switch all clocks of a power domain to a safe rate which is suitable
> for all possible voltages in order to ensure that hardware constraints
> aren't violated when power domain state toggles.
>
> Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
> Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124
> Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---
> drivers/soc/tegra/pmc.c | 92 ++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 90 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
> index f970b615ee27..a87645fac735 100644
> --- a/drivers/soc/tegra/pmc.c
> +++ b/drivers/soc/tegra/pmc.c
> @@ -237,6 +237,7 @@ struct tegra_powergate {
> unsigned int id;
> struct clk **clks;
> unsigned int num_clks;
> + unsigned long *clk_rates;
> struct reset_control *reset;
> };
>
> @@ -641,6 +642,57 @@ static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
> return 0;
> }
>
> +static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg)
> +{
> + unsigned long safe_rate = 100 * 1000 * 1000;
This seems a bit arbitrary. Where did you come up with that value?
I'm going to apply this to see how it fares in our testing.
Thierry
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next prev parent reply other threads:[~2021-03-25 14:39 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-02 12:24 [PATCH v4 0/5] Tegra PMC driver fixes and improvements Dmitry Osipenko
2021-03-02 12:24 ` [PATCH v4 1/5] soc/tegra: pmc: Fix imbalanced clock disabling in error code path Dmitry Osipenko
2021-03-25 14:27 ` Thierry Reding
2021-03-02 12:24 ` [PATCH v4 2/5] soc/tegra: pmc: Fix completion of power-gate toggling Dmitry Osipenko
2021-03-25 14:32 ` Thierry Reding
2021-03-02 12:25 ` [PATCH v4 3/5] soc/tegra: pmc: Ensure that clock rates aren't too high Dmitry Osipenko
2021-03-25 14:39 ` Thierry Reding [this message]
2021-03-25 15:02 ` Dmitry Osipenko
2021-03-25 15:05 ` Dmitry Osipenko
2021-03-02 12:25 ` [PATCH v4 4/5] soc/tegra: pmc: Print out domain name when reset fails to acquire Dmitry Osipenko
2021-03-25 14:40 ` Thierry Reding
2021-03-02 12:25 ` [PATCH v4 5/5] soc/tegra: pmc: Rate-limit error message about failed to acquire of reset Dmitry Osipenko
2021-03-25 14:42 ` Thierry Reding
2021-03-25 14:53 ` Dmitry Osipenko
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