From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.2 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C984C433E8 for ; Thu, 25 Mar 2021 14:50:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5FBC361A01 for ; Thu, 25 Mar 2021 14:50:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231308AbhCYOtj (ORCPT ); Thu, 25 Mar 2021 10:49:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229524AbhCYOt3 (ORCPT ); Thu, 25 Mar 2021 10:49:29 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 066DBC06174A; Thu, 25 Mar 2021 07:49:29 -0700 (PDT) Received: by mail-wm1-x335.google.com with SMTP id d191so1339297wmd.2; Thu, 25 Mar 2021 07:49:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=SWvMHK4Ot07NYjs1TXQxHKnMoJ0tlX8FET1AI29AVZg=; b=aqniE4xUchEMgXVFlAfySinuErd1wsZkzuNF6K0y8IG8kaOUIfUufGVbP3IwOq7GnO T9Cl8iG2I8LrPrRr8NxQrYQUY8BPqjphyCUSavaa+AxFXVBWbCmbgIXYRAZeSB3OgIKW VcIpoWqNHxtg7gQ8ND3tPbzTuRTFkMV0m0jBHM+Mm1F9XWeu/z0a6nupn2zHyhrbYvsQ kGthDsHIFeaOP8KDeYgmgdMx/0AFZfvXUuuX2Fg/9mpfBfGA6+uh7mxheCwsRshT4V8Z mp3bmeMOLAf1a6xMMoOxQKffBHOCxsHW+QOyqEu9omzRQsunSemHYf6VB8FYfq7uf1PT QXvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=SWvMHK4Ot07NYjs1TXQxHKnMoJ0tlX8FET1AI29AVZg=; b=FCoTfOKPeXcvGh0cM+fBTz+IuiEunmmrHQiddm/LUPseHI1k1O5JGUTLwRhBNG9K9W QKQTSGvuyFzMFtPYzVktevNgpwWMFFUEdHanVutqdnyfrdJw7ksBd3WhyejvOkuLgl+V 2OrNRqugTIn5kPHP4PGUKtDvDbsrS3XSzzVJkDIvQOhOByD5L+Vm84JgUHJBn+jMq/TR hbll0CR28weD9m4iRfUo3X8Dn3BufBqZ/ui5fF8AndKvTEwGkLsrE1d9sfO+SXfHIMMe kYDWq7GbtZhYApR2W+CVcIx3vyAFNLX6TeV44J26vmosX/9F+dkHUrmHTAAIcrIFi7vv QIcQ== X-Gm-Message-State: AOAM533/+Yq4076jn/R8Y4zr2h1Z+DjhJlNWClkYVVjbS/mZWyqBvGxi dIloYdGuymw3A+rL0rFkLTM= X-Google-Smtp-Source: ABdhPJxIjM6YO03HPGXR9x2Aq4ifABfHiBTvBqGsj9bs6OhqGRpc7VI3dZTXyRSRrsLs0/EtdBuZAg== X-Received: by 2002:a7b:c188:: with SMTP id y8mr8266237wmi.76.1616683767692; Thu, 25 Mar 2021 07:49:27 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id l9sm6259966wmq.2.2021.03.25.07.49.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Mar 2021 07:49:26 -0700 (PDT) Date: Thu, 25 Mar 2021 15:49:48 +0100 From: Thierry Reding To: Dmitry Osipenko Cc: Rob Herring , Jonathan Hunter , Mark Brown , Paul Fertser , Matt Merhar , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , =?utf-8?B?TWljaGHFgiBNaXJvc8WCYXc=?= , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 3/6] dt-bindings: power: tegra: Add binding for core power domain Message-ID: References: <20210314164810.26317-1-digetx@gmail.com> <20210314164810.26317-4-digetx@gmail.com> <20210323224826.GA1490612@robh.at.kernel.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="AKB8U57WCp8yhm9E" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/2.0.6 (98f8cb83) (2021-03-06) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --AKB8U57WCp8yhm9E Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Mar 24, 2021 at 02:01:29AM +0300, Dmitry Osipenko wrote: > 24.03.2021 01:48, Rob Herring =D0=BF=D0=B8=D1=88=D0=B5=D1=82: > > On Sun, Mar 14, 2021 at 07:48:07PM +0300, Dmitry Osipenko wrote: > >> All NVIDIA Tegra SoCs have a core power domain where majority of hardw= are > >> blocks reside. Add binding for the core power domain. > >> > >> Signed-off-by: Dmitry Osipenko > >> --- > >> .../power/nvidia,tegra20-core-domain.yaml | 51 +++++++++++++++++++ > >> 1 file changed, 51 insertions(+) > >> create mode 100644 Documentation/devicetree/bindings/power/nvidia,teg= ra20-core-domain.yaml > >> > >> diff --git a/Documentation/devicetree/bindings/power/nvidia,tegra20-co= re-domain.yaml b/Documentation/devicetree/bindings/power/nvidia,tegra20-cor= e-domain.yaml > >> new file mode 100644 > >> index 000000000000..4692489d780a > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/power/nvidia,tegra20-core-doma= in.yaml > >> @@ -0,0 +1,51 @@ > >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > >> +%YAML 1.2 > >> +--- > >> +$id: http://devicetree.org/schemas/power/nvidia,tegra20-core-domain.y= aml# > >> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >> + > >> +title: NVIDIA Tegra Core Power Domain > >> + > >> +maintainers: > >> + - Dmitry Osipenko > >> + - Jon Hunter > >> + - Thierry Reding > >> + > >> +allOf: > >> + - $ref: power-domain.yaml# > >> + > >> +properties: > >> + compatible: > >> + enum: > >> + - nvidia,tegra20-core-domain > >> + - nvidia,tegra30-core-domain > >> + > >> + operating-points-v2: > >> + description: > >> + Should contain level, voltages and opp-supported-hw property. > >> + The supported-hw is a bitfield indicating SoC speedo or process > >> + ID mask. > >> + > >> + "#power-domain-cells": > >> + const: 0 > >> + > >> + power-supply: > >> + description: > >> + Phandle to voltage regulator connected to the SoC Core power ra= il. > >> + > >> +required: > >> + - compatible > >> + - operating-points-v2 > >> + - "#power-domain-cells" > >> + - power-supply > >> + > >> +additionalProperties: false > >> + > >> +examples: > >> + - | > >> + power-domain { > >> + compatible =3D "nvidia,tegra20-core-domain"; > >> + operating-points-v2 =3D <&opp_table>; > >> + power-supply =3D <®ulator>; > >> + #power-domain-cells =3D <0>; > >=20 > > AFAICT, there's no way to access this 'hardware'? > correct To avoid exposing this "virtual" device in device tree, could this instead be modelled as a child node of the PMC node? We already expose a couple of generic power domains that way on Tegra210 and later, so perhaps some of that infrastructure can be reused? I suppose given that this is different from the standard powergate domains that we expose so far, this may need a different implementation, but from a device tree bindings point of view it could fit in with that. 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