From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CB59C433B4 for ; Wed, 7 Apr 2021 16:00:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0A06761382 for ; Wed, 7 Apr 2021 16:00:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354033AbhDGQAz (ORCPT ); Wed, 7 Apr 2021 12:00:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40166 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353992AbhDGQAr (ORCPT ); Wed, 7 Apr 2021 12:00:47 -0400 Received: from desiato.infradead.org (desiato.infradead.org [IPv6:2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E3A1C061760; Wed, 7 Apr 2021 09:00:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=In-Reply-To:Content-Transfer-Encoding: Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date: Sender:Reply-To:Content-ID:Content-Description; bh=H+ZMVpfa/CabsD8d5PA65uD38iRKxpv+RvDo3hX8JW0=; b=LI3JirhTB4v5sXB94brRFz4Bju Wx43cTRdICjBTwxuivVFW0b3J3HCgJtddI9O74+en4344IeBjDnThR37hrfvrEZpSdcZWUAlia37w p8ZNcMrV7gkhxpMv9YuImiWojpUnypK4nBh9hHAQtN9ibgSFzgip1Ga3/JPpJexePQU96Fpm1r5ux nG+hPED8h6w72ag7NjWKZAKLCbARHK68oucBf7/2he+6JNCoJpLIfcswTYvbJhNL2Sxvqzw39vKAr 3DE45L+ESAD1HHwGzWYzPLTvZGHimMkQxba/wWv557j2dih+BvU3gdgjywVdj+320u3rR6c7ho/vD pKL64eng==; Received: from j217100.upc-j.chello.nl ([24.132.217.100] helo=noisy.programming.kicks-ass.net) by desiato.infradead.org with esmtpsa (Exim 4.94 #2 (Red Hat Linux)) id 1lUAbH-005NDW-Kw; Wed, 07 Apr 2021 16:00:15 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id 002B73001FB; Wed, 7 Apr 2021 18:00:14 +0200 (CEST) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id E298B2BF09269; Wed, 7 Apr 2021 18:00:14 +0200 (CEST) Date: Wed, 7 Apr 2021 18:00:14 +0200 From: Peter Zijlstra To: Christoph =?iso-8859-1?Q?M=FCllner?= Cc: Christoph Hellwig , Guo Ren , linux-riscv , Linux Kernel Mailing List , linux-csky@vger.kernel.org, linux-arch , Guo Ren , Will Deacon , Ingo Molnar , Waiman Long , Arnd Bergmann , Anup Patel Subject: Re: [PATCH v4 3/4] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 Message-ID: References: <1616868399-82848-4-git-send-email-guoren@kernel.org> <20210407094224.GA3393992@infradead.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Apr 07, 2021 at 04:29:12PM +0200, Christoph Müllner wrote: > RISC-V defines LR/SC loops consisting of up to 16 instructions as > constrained LR/SC loops. Such constrained LR/SC loops provide the > required forward guarantees, that are expected (similar to what other > architectures, like AArch64, have). The text quoted by others didn't seem to say such a thing, but whatever. > What RISC-V does not have is sub-word atomics and if required, we > would have to implement them as LL/SC sequences. And yes, using atomic > instructions is preferred over using LL/SC, (psudo asm, can't be bothered to figure out the actual syntax) # setup r_and_mask, r_or_mask .L1 LL r, [word] AND r, r, r_and_mask OR r, r, r_or_mask SC r, [word] JNE .L1 is what you need for LL/SC based xchg16, that's less than 16 instructions. If RISC-V guarantees fwd progress on that, good, write it like that and lets end this thread. The fact that this is apparently hard, is not good.