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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id n25sm735157oop.13.2021.04.13.13.59.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Apr 2021 13:59:28 -0700 (PDT) Date: Tue, 13 Apr 2021 15:59:26 -0500 From: Bjorn Andersson To: Martin Blumenstingl Cc: linux-remoteproc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, ohad@wizery.com, robh+dt@kernel.org Subject: Re: [PATCH 3/5] dt-bindings: remoteproc: Add the documentation for Meson AO ARC rproc Message-ID: References: <20201230012724.1326156-1-martin.blumenstingl@googlemail.com> <20201230012724.1326156-4-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue 23 Mar 17:02 CDT 2021, Martin Blumenstingl wrote: > Hi Bjorn, > > On Thu, Mar 18, 2021 at 3:55 AM Bjorn Andersson > wrote: > [...] > > > +examples: > > > + - | > > > + remoteproc@1c { > > > + compatible= "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc"; > > > + reg = <0x1c 0x8>, <0x38 0x8>; > > > > I'm generally not in favor of mapping "individual" registers, do you > > know what hardware block this is part of? Can you express the whole > > block as an single entity in your DT? > the answer is unfortunately not easy :-) > > some background information: > Amlogic SoCs have two power domains: > - AO (Always-On) > - EE (Everything-Else) > > AO includes (at least) one ARC core for which this remoteproc dt-binding is. > EE includes ARM Cortex-A7/15/... cores > > The AO registers can be accessed from the EE power-domain and vice versa > > Following is an extract (with comments added by me) for the AO > registers (taken from the GPL vendor kernel): > #define AO_RTI_STATUS_REG0 ((0x00 << 10) | (0x00 << 2)) > #define AO_RTI_STATUS_REG1 ((0x00 << 10) | (0x01 << 2)) > #define AO_RTI_STATUS_REG2 ((0x00 << 10) | (0x02 << 2)) > these three are used for communication with the firmware on the AO ARC core > I am not sure into which Linux subsystem these would fit into best > > #define AO_RTI_PWR_CNTL_REG1 ((0x00 << 10) | (0x03 << 2)) > #define AO_RTI_PWR_CNTL_REG0 ((0x00 << 10) | (0x04 << 2)) > this includes various power-domains for the following functionality > (and probably more): > - DDR PHY I/O > - AHB SRAM > - video encoder/decoders > - EE domain isolation > > #define AO_RTI_PIN_MUX_REG ((0x00 << 10) | (0x05 << 2)) > first part of the pin controller registers for the "AO" bank pads > this includes various GPIOs, UART, I2C for communication with a PMIC, > infrared remote decoder, two PWMs, etc. > all (known) functionality can be used by Linux as well. > especially the UART, I2C, IR decoder and GPIOs are functionality that > we use with Linux today - without involving the AO ARC > remote-processor. > > #define AO_WD_GPIO_REG ((0x00 << 10) | (0x06 << 2)) > (I think this is related to the watchdog being able to trigger the > SoC's reset line, but there's no documentation on this register) > > #define AO_REMAP_REG0 ((0x00 << 10) | (0x07 << 2)) > #define AO_REMAP_REG1 ((0x00 << 10) | (0x08 << 2)) > remap registers for the AO ARC remote-processor as used in this binding > > #define AO_GPIO_O_EN_N ((0x00 << 10) | (0x09 << 2)) > #define AO_GPIO_I ((0x00 << 10) | (0x0A << 2)) > GPIO controller registers for the "AO" bank pads > > #define AO_RTI_PULL_UP_REG ((0x00 << 10) | (0x0B << 2)) > second part of the pin controller registers for the "AO" bank pads > > #define AO_RTI_WD_MARK ((0x00 << 10) | (0x0D << 2)) > again, I think this is somehow related to the watchdog but there's no > documentation on this > > #define AO_CPU_CNTL ((0x00 << 10) | (0x0E << 2)) > #define AO_CPU_STAT ((0x00 << 10) | (0x0F << 2)) > used for booting the AO ARC remote-processor > > #define AO_RTI_GEN_CNTL_REG0 ((0x00 << 10) | (0x10 << 2)) > seems to be a multi purpose register as it (seems to) contains some > reset bits (for the AO UART and RTC) - not documented > > (more registers are following) > > to summarize this: I think there's indeed three different sets of registers > having one big device-tree node spanning all of these registers seems > incorrect to me as the other IPs are independent of the AO ARC > remote-processor. > so the way I have done it in the original patch is the best I could > come up with. > > Please let me know what you think! > I see. Describing these kinds blocks in DT is indeed tricky, I've had both cases where a block maps to multiple "functions" or where they contain misc registers to be used in relation to some other block. The prior typically lends itself to be modelled as a "simple-mfd" and the latter as a "syscon". So perhaps you could do a simple-mfd that spans the entire block and then describe the remoteproc, watchdog?, pinctrl pieces as children under that? Regards, Bjorn