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[93.35.189.2]) by smtp.gmail.com with ESMTPSA id b7sm16414063wri.83.2021.05.08.18.17.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 May 2021 18:17:31 -0700 (PDT) Date: Sun, 9 May 2021 03:17:23 +0200 From: Ansuel Smith To: Andrew Lunn Cc: Florian Fainelli , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH net-next v4 19/28] net: dsa: qca8k: make rgmii delay configurable Message-ID: References: <20210508002920.19945-1-ansuelsmth@gmail.com> <20210508002920.19945-19-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, May 09, 2021 at 03:07:15AM +0200, Andrew Lunn wrote: > On Sun, May 09, 2021 at 01:58:07AM +0200, Ansuel Smith wrote: > > On Sat, May 08, 2021 at 08:12:26PM +0200, Andrew Lunn wrote: > > > > + > > > > + /* Assume only one port with rgmii-id mode */ > > > > > > Since this is only valid for the RGMII port, please look in that > > > specific node for these properties. > > > > > > Andrew > > > > Sorry, can you clarify this? You mean that I should check in the phandle > > pointed by the phy-handle or that I should modify the logic to only > > check for one (and the unique in this case) rgmii port? > > Despite there only being one register, it should be a property of the > port. If future chips have multiple RGMII ports, i expect there will > be multiple registers. To avoid confusion in the future, we should > make this a proper to the port it applies to. So assuming the RGMII > port is port 0: > > #address-cells = <1>; > #size-cells = <0>; > port@0 { > reg = <0>; > label = "cpu"; > ethernet = <&gmac1>; > phy-mode = "rgmii"; > fixed-link { > speed = 1000; > full-duplex; > }; > rx-internal-delay-ps = <2000>; > tx-internal-delay-ps = <2000>; > }; > > port@1 { > reg = <1>; > label = "lan1"; > phy-handle = <&phy_port1>; > }; > > port@2 { > reg = <2>; > label = "lan2"; > phy-handle = <&phy_port2>; > }; > > port@3 { > reg = <3>; > label = "lan3"; > phy-handle = <&phy_port3>; > }; > > port@4 { > reg = <4>; > label = "lan4"; > phy-handle = <&phy_port4>; > }; > > port@5 { > reg = <5>; > label = "wan"; > phy-handle = <&phy_port5>; > }; > }; > }; > }; > > You also should validate that phy-mode is rgmii and only rgmii. You > get into odd situations if it is any of the other three rgmii modes. > > Andrew And that is the intention of the port. I didn't want the binding to be set on the switch node but on the rgmii node. Correct me if I'm wrong but isn't what this patch already do? In of_rgmii_delay I get the ports node of the current switch, iterate every port, find the one with the phy-mode set to "rgmii-id" and check if it's present any value. And save the value in the priv struct. The actual delay is applied in the phylink_mac_config only if the mode is set to rgmii-id. (the current code set by default a delay of 3000 with rgmii-id, so this is just to make this value configurable)