From: Greg KH <gregkh@linuxfoundation.org>
To: Palmer Dabbelt <palmerdabbelt@google.com>
Cc: pbonzini@redhat.com, anup@brainfault.org,
Anup Patel <Anup.Patel@wdc.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
aou@eecs.berkeley.edu, corbet@lwn.net, graf@amazon.com,
Atish Patra <Atish.Patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Damien Le Moal <Damien.LeMoal@wdc.com>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev
Subject: Re: [PATCH v18 00/18] KVM RISC-V Support
Date: Fri, 21 May 2021 20:25:23 +0200 [thread overview]
Message-ID: <YKf7E4YfLrcfgCoi@kroah.com> (raw)
In-Reply-To: <mhng-122345f7-47d9-4509-8ae6-ce1da912fc00@palmerdabbelt-glaptop>
On Fri, May 21, 2021 at 11:08:15AM -0700, Palmer Dabbelt wrote:
> On Fri, 21 May 2021 10:47:51 PDT (-0700), Greg KH wrote:
> > On Fri, May 21, 2021 at 07:21:12PM +0200, Paolo Bonzini wrote:
> > > On 21/05/21 19:13, Palmer Dabbelt wrote:
> > > > >
> > > >
> > > > I don't view this code as being in a state where it can be
> > > > maintained, at least to the standards we generally set within the
> > > > kernel. The ISA extension in question is still subject to change, it
> > > > says so right at the top of the H extension <https://github.com/riscv/riscv-isa-manual/blob/master/src/hypervisor.tex#L4>
> > > >
> > > > {\bf Warning! This draft specification may change before being
> > > > accepted as standard by the RISC-V Foundation.}
> > >
> > > To give a complete picture, the last three relevant changes have been in
> > > August 2019, November 2019 and May 2020. It seems pretty frozen to me.
> > >
> > > In any case, I think it's clear from the experience with Android that
> > > the acceptance policy cannot succeed. The only thing that such a policy
> > > guarantees, is that vendors will use more out-of-tree code. Keeping a
> > > fully-developed feature out-of-tree for years is not how Linux is run.
> > >
> > > > I'm not sure where exactly the line for real hardware is, but for
> > > > something like this it would at least involve some chip that is
> > > > widely availiable and needs the H extension to be useful
> > >
> > > Anup said that "quite a few people have already implemented RISC-V
> > > H-extension in hardware as well and KVM RISC-V works on real HW as well".
> > > Those people would benefit from having KVM in the Linus tree.
> >
> > Great, but is this really true? If so, what hardware has this? I have
> > a new RISC-V device right here next to me, what would I need to do to
> > see if this is supported in it or not?
>
> You can probe the misa register, it should have the H bit set if it supports
> the H extension.
To let everyone know, based on our private chat we had off-list, no, the
device I have does not support this extension, so unless someone can
point me at real hardware, I don't think this code needs to be
considered for merging anywhere just yet.
thanks,
greg k-h
next prev parent reply other threads:[~2021-05-21 18:25 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-19 3:35 [PATCH v18 00/18] KVM RISC-V Support Anup Patel
2021-05-19 3:35 ` [PATCH v18 01/18] RISC-V: Add hypervisor extension related CSR defines Anup Patel
2021-05-19 3:35 ` [PATCH v18 02/18] RISC-V: Add initial skeletal KVM support Anup Patel
2021-05-19 9:24 ` Dan Carpenter
2021-05-19 10:17 ` Dan Carpenter
2021-05-19 3:35 ` [PATCH v18 03/18] RISC-V: KVM: Implement VCPU create, init and destroy functions Anup Patel
2021-05-19 3:35 ` [PATCH v18 04/18] RISC-V: KVM: Implement VCPU interrupts and requests handling Anup Patel
2021-05-19 3:35 ` [PATCH v18 05/18] RISC-V: KVM: Implement KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls Anup Patel
2021-05-19 3:35 ` [PATCH v18 06/18] RISC-V: KVM: Implement VCPU world-switch Anup Patel
2021-05-19 3:35 ` [PATCH v18 07/18] RISC-V: KVM: Handle MMIO exits for VCPU Anup Patel
2021-05-19 3:35 ` [PATCH v18 08/18] RISC-V: KVM: Handle WFI " Anup Patel
2021-05-19 3:35 ` [PATCH v18 09/18] RISC-V: KVM: Implement VMID allocator Anup Patel
2021-05-19 3:35 ` [PATCH v18 10/18] RISC-V: KVM: Implement stage2 page table programming Anup Patel
2021-05-19 3:35 ` [PATCH v18 11/18] RISC-V: KVM: Implement MMU notifiers Anup Patel
2021-05-19 10:09 ` Dan Carpenter
2021-05-19 3:35 ` [PATCH v18 12/18] RISC-V: KVM: Add timer functionality Anup Patel
2021-05-19 3:35 ` [PATCH v18 13/18] RISC-V: KVM: FP lazy save/restore Anup Patel
2021-05-19 3:35 ` [PATCH v18 14/18] RISC-V: KVM: Implement ONE REG interface for FP registers Anup Patel
2021-05-19 10:11 ` Dan Carpenter
2021-05-20 6:09 ` Dan Carpenter
2021-05-19 3:35 ` [PATCH v18 15/18] RISC-V: KVM: Add SBI v0.1 support Anup Patel
2021-05-19 3:35 ` [PATCH v18 16/18] RISC-V: KVM: Document RISC-V specific parts of KVM API Anup Patel
2021-05-19 3:35 ` [PATCH v18 17/18] RISC-V: KVM: Move sources to drivers/staging directory Anup Patel
2021-05-19 3:35 ` [PATCH v18 18/18] RISC-V: KVM: Add MAINTAINERS entry Anup Patel
2021-05-19 4:58 ` [PATCH v18 00/18] KVM RISC-V Support Greg Kroah-Hartman
2021-05-19 5:10 ` Anup Patel
2021-05-19 5:21 ` Greg Kroah-Hartman
2021-05-19 10:47 ` Greg Kroah-Hartman
2021-05-19 11:18 ` Paolo Bonzini
2021-05-19 12:23 ` Greg Kroah-Hartman
2021-05-19 13:29 ` Paolo Bonzini
2021-05-19 13:58 ` Greg Kroah-Hartman
2021-05-19 15:08 ` Dan Carpenter
2021-05-19 15:26 ` Paolo Bonzini
2021-05-21 17:13 ` Palmer Dabbelt
2021-05-21 17:21 ` Paolo Bonzini
2021-05-21 17:47 ` Greg KH
2021-05-21 18:08 ` Palmer Dabbelt
2021-05-21 18:25 ` Greg KH [this message]
2021-05-21 20:25 ` Paolo Bonzini
2021-05-24 7:09 ` Guo Ren
2021-05-24 22:57 ` Palmer Dabbelt
2021-05-24 23:08 ` Damien Le Moal
2021-05-25 7:37 ` Greg KH
2021-05-25 8:01 ` Damien Le Moal
2021-05-25 8:11 ` Greg KH
2021-05-25 8:24 ` Paolo Bonzini
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