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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id 15sm2571809oij.26.2021.06.07.16.31.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 16:31:49 -0700 (PDT) Date: Mon, 7 Jun 2021 18:31:47 -0500 From: Bjorn Andersson To: khsieh@codeaurora.org, swboyd@chromium.org Cc: robdclark@gmail.com, sean@poorly.run, vkoul@kernel.org, agross@kernel.org, robh+dt@kernel.org, devicetree@vger.kernel.org, abhinavk@codeaurora.org, aravindh@codeaurora.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] arm64/dts/qcom/sc7180: Add Display Port dt node Message-ID: References: <1622736555-15775-1-git-send-email-khsieh@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon 07 Jun 12:48 CDT 2021, khsieh@codeaurora.org wrote: > On 2021-06-05 22:07, Bjorn Andersson wrote: > > On Thu 03 Jun 16:56 CDT 2021, khsieh@codeaurora.org wrote: > > > > > On 2021-06-03 09:53, Bjorn Andersson wrote: > > > > On Thu 03 Jun 11:09 CDT 2021, Kuogee Hsieh wrote: > > [..] > > > > > diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi > > [..] > > > > > + power-domains = <&rpmhpd SC7180_CX>; > > > > > > > > Just curious, but isn't the DP block in the MDSS_GDCS? Or do we need to > > > > mention CX here in order for the opp framework to apply required-opps > > > > of CX? > > > > > > yes, > > > > If you want me, or other maintainers, to spend any time reviewing or > > applying your patches going forward then you need to actually bother > > replying properly to the questions asked. > > > > Thanks, > > Bjorn > > Sorry about the confusion. What I meant is that even though DP controller is > in the MDSS_GDSC > power domain, DP PHY/PLL sources out of CX. The DP link clocks have a direct > impact > on the CX voltage corners. Therefore, we need to mention the CX power domain > here. And, since > we can associate only one OPP table with one device, we picked the DP link > clock over other > clocks. Thank you, that's a much more useful answer. Naturally I would think it would make more sense for the PHY/PLL driver to ensure that CX is appropriately voted for then, but I think that would result in it being the clock driver performing such vote and I'm unsure how the opp table for that would look. @Stephen, what do you say? Regards, Bjorn