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[35.247.111.240]) by smtp.gmail.com with ESMTPSA id n6sm2520661pgm.79.2021.06.04.09.48.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:48:03 -0700 (PDT) Date: Fri, 4 Jun 2021 16:48:00 +0000 From: Sean Christopherson To: Cody Yao-oc Cc: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@redhat.com, namhyung@kernel.org, tglx@linutronix.de, bp@alien8.de, hpa@zytor.com, x86@kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] x86/perf: Fixed obtaining address error about performance monitor MSR on old Inel CPU. Message-ID: References: <20210604055438.17705-1-CodyYao-oc@zhaoxin.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210604055438.17705-1-CodyYao-oc@zhaoxin.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jun 04, 2021, Cody Yao-oc wrote: > From: CodyYao-oc > > Fix "obtain wrong msr address" bug in function nmi_perfctr_msr_to_bit > and nmi_eventsel_msr_to_bit. In X86_VENDOR_INTEL switch branch, if all > of the check conditions are not met, code flow will slip to > X86_VENDOR_ZHAOXIN branch which may lead to incorrect information. > > Therefore, "fallthrough" should be changed to "break" to avoid it. This should explicitly state that using fallthrough instead of break was completely unintentional, assuming that's indeed the case. Fixes: 3a4ac121c2ca ("x86/perf: Add hardware performance events support for Zhaoxin CPU.") > Signed-off-by: CodyYao-oc > --- > arch/x86/kernel/cpu/perfctr-watchdog.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c > index 3ef5868ac588..7aecb2fc3186 100644 > --- a/arch/x86/kernel/cpu/perfctr-watchdog.c > +++ b/arch/x86/kernel/cpu/perfctr-watchdog.c > @@ -63,7 +63,7 @@ static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr) > case 15: > return msr - MSR_P4_BPU_PERFCTR0; > } > - fallthrough; > + break; > case X86_VENDOR_ZHAOXIN: > case X86_VENDOR_CENTAUR: > return msr - MSR_ARCH_PERFMON_PERFCTR0; > @@ -96,7 +96,7 @@ static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr) > case 15: > return msr - MSR_P4_BSU_ESCR0; > } > - fallthrough; > + break; > case X86_VENDOR_ZHAOXIN: > case X86_VENDOR_CENTAUR: > return msr - MSR_ARCH_PERFMON_EVENTSEL0; > -- > 2.17.1 >