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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id i15sm63109ots.39.2021.06.15.14.57.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 14:57:30 -0700 (PDT) Date: Tue, 15 Jun 2021 16:57:28 -0500 From: Bjorn Andersson To: Rob Herring Cc: Manivannan Sadhasivam , Lorenzo Pieralisi , Bjorn Helgaas , linux-arm-msm , PCI , devicetree@vger.kernel.org, "linux-kernel@vger.kernel.org" , Siddartha Mohanadoss Subject: Re: [PATCH v2 2/3] PCI: dwc: Add Qualcomm PCIe Endpoint controller driver Message-ID: References: <20210603103814.95177-1-manivannan.sadhasivam@linaro.org> <20210603103814.95177-3-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue 15 Jun 16:40 CDT 2021, Rob Herring wrote: > On Sat, Jun 5, 2021 at 9:07 PM Bjorn Andersson > wrote: > > > > On Thu 03 Jun 05:38 CDT 2021, Manivannan Sadhasivam wrote: > > > > > Add driver support for Qualcomm PCIe Endpoint controller driver based on > > > the Designware core with added Qualcomm specific wrapper around the > > > core. The driver support is very basic such that it supports only > > > enumeration, PCIe read/write, and MSI. There is no ASPM and PM support > > > for now but these will be added later. > > > > > > The driver is capable of using the PERST# and WAKE# side-band GPIOs for > > > operation and written on top of the DWC PCI framework. > > > > > > Co-developed-by: Siddartha Mohanadoss > > > Signed-off-by: Siddartha Mohanadoss > > > [mani: restructured the driver and fixed several bugs for upstream] > > > Signed-off-by: Manivannan Sadhasivam > > > > Really nice to see this working! > > [...] > > > > +static void qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep *pcie_ep) > > > +{ > > > + writel_relaxed(0x0, pcie_ep->tcsr + TCSR_PCIE_PERST_EN); > > > > Please avoid _relaxed accessor unless there's a strong reason, and if so > > document it. > > Uhhh, what!? That's the wrong way around from what I've ever seen > anyone say. Have you ever looked at the resulting code on arm32 with > OMAP enabled? It's just a memory barrier and an indirect function call > on every access. > > Use readl/writel if you have an ordering requirement WRT DMA, > otherwise use relaxed variants. > That does make sense. Unfortunately I don't know where this started, but I would guess it might have been a reaction to the fact that people where just sprinkling wmb() all over the place to be on the safe side... > > > + writel_relaxed(0x0, pcie_ep->tcsr + TCSR_PERST_SEPARATION_ENABLE); > > > +} > > > + > > [...] > > > > +static struct platform_driver qcom_pcie_ep_driver = { > > > + .probe = qcom_pcie_ep_probe, > > > + .driver = { > > > + .name = "qcom-pcie-ep", > > > > Skip the indentation of the '='. > > > > > + .suppress_bind_attrs = true, > > > > Why do we suppress_bind_attrs? > > Because remove is not handled. > Not handled in Mani's driver, or is this a PCI thing? Regards, Bjorn