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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id v20sm1884581ooe.47.2021.06.18.10.35.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Jun 2021 10:35:32 -0700 (PDT) Date: Fri, 18 Jun 2021 12:35:30 -0500 From: Bjorn Andersson To: Konrad Dybcio Cc: Bhupesh Sharma , linux-arm-msm@vger.kernel.org, bhupesh.linux@gmail.com, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, agross@kernel.org, Mark Brown , Vinod Koul Subject: Re: [PATCH v3 4/5] arm64: dts: qcom: pmm8155au_2: Add base dts file Message-ID: References: <20210617054548.353293-1-bhupesh.sharma@linaro.org> <20210617054548.353293-5-bhupesh.sharma@linaro.org> <6011130d-8ce8-420b-6e55-5d168fef0347@somainline.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <6011130d-8ce8-420b-6e55-5d168fef0347@somainline.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu 17 Jun 17:32 CDT 2021, Konrad Dybcio wrote: > > > Add base DTS file for pmm8155au_2 along with GPIOs, power-on, rtc and vadc > > nodes. > > > > Cc: Mark Brown > > Cc: Vinod Koul > > Reviewed-by: Bjorn Andersson > > Signed-off-by: Bhupesh Sharma > > --- > > arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi | 107 ++++++++++++++++++++++ > > 1 file changed, 107 insertions(+) > > create mode 100644 arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi > > > > diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi > > new file mode 100644 > > index 000000000000..0c7d7a66c0b5 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi > > @@ -0,0 +1,107 @@ > > +// SPDX-License-Identifier: BSD-3-Clause > > +/* > > + * Copyright (c) 2021, Linaro Limited > > + */ > > + > > +#include > > +#include > > +#include > > + > > +/ { > > + thermal-zones { > > + pmm8155au-2-thermal { > > + polling-delay-passive = <100>; > > + polling-delay = <0>; > > + > > + thermal-sensors = <&pmm8155au_2_temp>; > > + > > + trips { > > + trip0 { > > + temperature = <95000>; > > + hysteresis = <0>; > > + type = "passive"; > > + }; > > + > > + trip1 { > > + temperature = <115000>; > > + hysteresis = <0>; > > + type = "hot"; > > + }; > > + > > + trip2 { > > + temperature = <145000>; > > + hysteresis = <0>; > > + type = "critical"; > > + }; > > + }; > > + }; > > + }; > > +}; > > + > > +&spmi_bus { > > + pmic@4 { > > + compatible = "qcom,pmm8155au", "qcom,spmi-pmic"; > > + reg = <0x4 SPMI_USID>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + power-on@800 { > > + compatible = "qcom,pm8916-pon"; > > + reg = <0x0800>; > > No common debounce, interrupts, bias- property or pwrkey key code? > > Besides, (as a question to Bjorn and others) do we pad reg to 4 digits in PMIC DTs now? > We want the regs to be padded to the address width to make it easier for humans to sort the nodes. At least for me it's easy to compare a 3-digit address with a 4-digit one, so I haven't felt the need to enforce it here. But I certainly don't mind. > > > > + > > + status = "disabled"; > > + }; > > + > > + pmm8155au_2_temp: temp-alarm@2400 { > > + compatible = "qcom,spmi-temp-alarm"; > > + reg = <0x2400>; > > + interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; > > + io-channels = <&pmm8155au_2_adc ADC5_DIE_TEMP>; > > + io-channel-names = "thermal"; > > + #thermal-sensor-cells = <0>; > > + }; > > + > > + pmm8155au_2_adc: adc@3100 { > > + compatible = "qcom,spmi-adc5"; > > + reg = <0x3100>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + #io-channel-cells = <1>; > > + interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; > > + > > + ref-gnd@0 { > > + reg = ; > > + qcom,pre-scaling = <1 1>; > > + label = "ref_gnd"; > > + }; > > + > > + vref-1p25@1 { > > + reg = ; > > + qcom,pre-scaling = <1 1>; > > + label = "vref_1p25"; > > + }; > > + > > + die-temp@6 { > > + reg = ; > > + qcom,pre-scaling = <1 1>; > > + label = "die_temp"; > > + }; > > + }; > > + > > + pmm8155au_2_gpios: gpio@c000 { > > + compatible = "qcom,pmm8155au-gpio"; > > + reg = <0xc000>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + }; > > Don't we do gpio-ranges anymore? > Yes, that is required by the binding. I added that and picked up the 3 patches. Thanks for reviewing Konrad, and thanks for the patches Bhupesh. Regards, Bjorn > > > > + }; > > + > > + pmic@5 { > > + compatible = "qcom,pmm8155au", "qcom,spmi-pmic"; > > + reg = <0x5 SPMI_USID>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > +}; > > > Konrad >