From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C68A8C48BC2 for ; Mon, 21 Jun 2021 17:59:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AB8F361289 for ; Mon, 21 Jun 2021 17:59:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233239AbhFUSBM (ORCPT ); Mon, 21 Jun 2021 14:01:12 -0400 Received: from perceval.ideasonboard.com ([213.167.242.64]:58254 "EHLO perceval.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233161AbhFUR6b (ORCPT ); Mon, 21 Jun 2021 13:58:31 -0400 Received: from pendragon.ideasonboard.com (62-78-145-57.bb.dnainternet.fi [62.78.145.57]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 654F75E17; Mon, 21 Jun 2021 19:56:14 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1624298174; bh=xTAY6XehRVOvS40XWKwQ0ZxduxmilFWHgm+B43wpOtk=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=LfWdClqW2kQ6uB7QoP6STkQ08ylCf9woPfaGaApNrjNI6NChKCGJenjYRIPetky1q JKwS5IDWB0LO3DvoiZU03U6xpabHxbwPjne9FRGYCZgyhptOLomgX7XSSO+u9YzUiY d6WEo81pq6a8aUgM+XvgzDhTE2t7Dw2Nxe2Gc7R0= Date: Mon, 21 Jun 2021 20:55:48 +0300 From: Laurent Pinchart To: Jagan Teki Cc: Peng Fan , Shawn Guo , Sascha Hauer , Tomasz Figa , Fancy Fang , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, NXP Linux Team , linux-amarula@amarulasolutions.com, Anthony Brandon , Francis Laniel , Matteo Lisi , Milco Pratesi , Andrzej Hajda , Neil Armstrong , Robert Foss , Rob Herring Subject: Re: [RFC PATCH 1/9] dt-bindings: display: bridge: Add Samsung SEC MIPI DSIM bindings Message-ID: References: <20210621072424.111733-1-jagan@amarulasolutions.com> <20210621072424.111733-2-jagan@amarulasolutions.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20210621072424.111733-2-jagan@amarulasolutions.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jagan, Thank you for the patch. On Mon, Jun 21, 2021 at 12:54:16PM +0530, Jagan Teki wrote: > Samsung SEC MIPI DSIM Bridge controller is MIPI DSI bridge > available in NXP's i.MX8M Mini and Nano Processors. > > Add dt-bingings for it. > > Cc: Andrzej Hajda > Cc: Neil Armstrong > Cc: Robert Foss > Cc: Laurent Pinchart > Cc: Rob Herring > Signed-off-by: Jagan Teki > --- > .../display/bridge/samsung,sec-dsim.yaml | 184 ++++++++++++++++++ > 1 file changed, 184 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.yaml > > diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.yaml > new file mode 100644 > index 000000000000..32f67f313dfd > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.yaml > @@ -0,0 +1,184 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/bridge/samsung,sec-dsim.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Samsung SEC MIPI DSIM Bridge controller on i.MX8M Mini and Nano SoCs > + > +maintainers: > + - Jagan Teki > + > +description: | > + NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for > + the SOCs NWL MIPI-DSI host controller. > + > +allOf: > + - $ref: ../dsi-controller.yaml# > + > +properties: > + compatible: > + enum: > + - fsl,imx8mm-sec-dsim > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > + assigned-clock-parents: true > + assigned-clock-rates: true > + assigned-clocks: true > + > + clocks: > + items: > + - description: DSI bus clock > + - description: PHY_REF clock > + > + clock-names: > + items: > + - const: bus > + - const: phy_ref > + > + phys: > + maxItems: 1 > + description: phandle to the phy module representing the DPHY > + > + phy-names: > + items: > + - const: dphy > + > + power-domains: > + maxItems: 1 > + description: phandle to the associated power domain > + > + samsung,burst-clock-frequency: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + DSIM high speed burst mode frequency. > + > + samsung,esc-clock-frequency: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + DSIM escape mode frequency. > + > + samsung,pll-clock-frequency: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + DSIM oscillator clock frequency. Why do you need those three properties ? They look like configuration information to me, not system description. If they are needed, their description needs to explain how to set them. Looking at the three descriptions above I have no idea what to select for those frequencies. > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/$defs/port-base > + description: > + Input port node to receive pixel data from the > + display controller. Exactly one endpoint must be > + specified. > + properties: > + endpoint@0: > + $ref: /schemas/graph.yaml#/properties/endpoint > + description: sub-node describing the input from LCDIF > + > + endpoint@1: > + $ref: /schemas/graph.yaml#/properties/endpoint > + description: sub-node describing the input from DCSS > + > + oneOf: > + - required: > + - endpoint@0 > + - required: > + - endpoint@1 > + > + unevaluatedProperties: false > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + DSI output port node to the panel or the next bridge > + in the chain > + > + required: > + - port@0 > + - port@1 > + > +required: > + - '#address-cells' > + - '#size-cells' > + - clock-names > + - clocks > + - compatible > + - interrupts > + - phy-names > + - phys > + - ports > + - reg > + - samsung,burst-clock-frequency > + - samsung,esc-clock-frequency > + - samsung,pll-clock-frequency > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + > + dsi: dsi@32e10000 { > + compatible = "fsl,imx8mm-sec-dsim"; > + reg = <0x32e10000 0xa0>; > + clocks = <&clk IMX8MM_CLK_DSI_CORE>, > + <&clk IMX8MM_CLK_DSI_PHY_REF>; > + clock-names = "bus", "phy_ref"; > + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, > + <&clk IMX8MM_VIDEO_PLL1_OUT>, > + <&clk IMX8MM_CLK_DSI_PHY_REF>; > + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, > + <&clk IMX8MM_VIDEO_PLL1_BYPASS>, > + <&clk IMX8MM_VIDEO_PLL1_OUT>; > + assigned-clock-rates = <266000000>, <594000000>, <27000000>; > + interrupts = ; > + phys = <&dphy>; > + phy-names = "dphy"; > + power-domains = <&dispmix_blk_ctl IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DSI>; > + samsung,burst-clock-frequency = <891000000>; > + samsung,esc-clock-frequency = <54000000>; > + samsung,pll-clock-frequency = <27000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + #size-cells = <0>; > + #address-cells = <1>; > + > + dsi_in_lcdif: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&lcdif_out_dsi>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + dsi_out_panel: endpoint { > + remote-endpoint = <&panel_in_dsi>; > + }; > + }; > + }; > + }; -- Regards, Laurent Pinchart