From: Matthias Kaehlcke <mka@chromium.org>
To: Thara Gopinath <thara.gopinath@linaro.org>
Cc: agross@kernel.org, bjorn.andersson@linaro.org,
rui.zhang@intel.com, daniel.lezcano@linaro.org,
viresh.kumar@linaro.org, rjw@rjwysocki.net, robh+dt@kernel.org,
linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [Patch v2 1/5] firmware: qcom_scm: Introduce SCM calls to access LMh
Date: Thu, 24 Jun 2021 10:48:36 -0700 [thread overview]
Message-ID: <YNTFdCPU2saMCT/y@google.com> (raw)
In-Reply-To: <20210624115813.3613290-2-thara.gopinath@linaro.org>
On Thu, Jun 24, 2021 at 07:58:09AM -0400, Thara Gopinath wrote:
> Introduce SCM calls to access/configure limits management hardware(LMH).
>
> Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
> ---
>
> v1->v2:
> Changed the input parameters in qcom_scm_lmh_dcvsh from payload_buf and
> payload_size to payload_fn, payload_reg, payload_val as per Bjorn's review
> comments.
>
> drivers/firmware/qcom_scm.c | 54 +++++++++++++++++++++++++++++++++++++
> drivers/firmware/qcom_scm.h | 4 +++
> include/linux/qcom_scm.h | 14 ++++++++++
> 3 files changed, 72 insertions(+)
>
> diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
> index ee9cb545e73b..19e9fb91d084 100644
> --- a/drivers/firmware/qcom_scm.c
> +++ b/drivers/firmware/qcom_scm.c
> @@ -1147,6 +1147,60 @@ int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
> }
> EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle);
>
> +bool qcom_scm_lmh_dcvsh_available(void)
> +{
> + return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_LMH, QCOM_SCM_LMH_LIMIT_DCVSH);
> +}
> +EXPORT_SYMBOL(qcom_scm_lmh_dcvsh_available);
> +
> +int qcom_scm_lmh_profile_change(u32 profile_id)
> +{
> + struct qcom_scm_desc desc = {
> + .svc = QCOM_SCM_SVC_LMH,
> + .cmd = QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE,
> + .arginfo = QCOM_SCM_ARGS(1, QCOM_SCM_VAL),
> + .args[0] = profile_id,
> + .owner = ARM_SMCCC_OWNER_SIP,
> + };
> +
> + return qcom_scm_call(__scm->dev, &desc, NULL);
> +}
> +EXPORT_SYMBOL(qcom_scm_lmh_profile_change);
> +
> +int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
> + u64 limit_node, u32 node_id, u64 version)
> +{
> + dma_addr_t payload_phys;
> + u32 *payload_buf;
> + int payload_size = 5 * sizeof(u32);
> +
> + struct qcom_scm_desc desc = {
> + .svc = QCOM_SCM_SVC_LMH,
> + .cmd = QCOM_SCM_LMH_LIMIT_DCVSH,
> + .arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_VAL,
> + QCOM_SCM_VAL, QCOM_SCM_VAL),
> + .args[1] = payload_size,
> + .args[2] = limit_node,
> + .args[3] = node_id,
> + .args[4] = version,
> + .owner = ARM_SMCCC_OWNER_SIP,
> + };
> +
> + payload_buf = dma_alloc_coherent(__scm->dev, payload_size, &payload_phys, GFP_KERNEL);
> + if (!payload_buf)
> + return -ENOMEM;
> +
> + payload_buf[0] = payload_fn;
> + payload_buf[1] = 0;
> + payload_buf[2] = payload_reg;
> + payload_buf[3] = 1;
> + payload_buf[4] = payload_val;
> +
> + desc.args[0] = payload_phys;
> + return qcom_scm_call(__scm->dev, &desc, NULL);
dma_free_coherent()?
next prev parent reply other threads:[~2021-06-24 17:48 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-24 11:58 [Patch v2 0/5] Introduce LMh driver for Qualcomm SoCs Thara Gopinath
2021-06-24 11:58 ` [Patch v2 1/5] firmware: qcom_scm: Introduce SCM calls to access LMh Thara Gopinath
2021-06-24 17:48 ` Matthias Kaehlcke [this message]
2021-06-25 15:45 ` Thara Gopinath
2021-06-24 11:58 ` [Patch v2 2/5] thermal: qcom: Add support for LMh driver Thara Gopinath
2021-06-24 17:24 ` Matthias Kaehlcke
2021-06-30 3:06 ` Thara Gopinath
2021-06-24 11:58 ` [Patch v2 3/5] cpufreq: qcom-cpufreq-hw: Add dcvs interrupt support Thara Gopinath
2021-06-29 2:35 ` Viresh Kumar
2021-06-30 2:25 ` Thara Gopinath
2021-06-30 3:53 ` Viresh Kumar
2021-06-29 2:50 ` Taniya Das
2021-06-30 2:27 ` Thara Gopinath
2021-06-24 11:58 ` [Patch v2 4/5] arm64: boot: dts: qcom: sdm45: Add support for LMh node Thara Gopinath
2021-06-24 11:58 ` [Patch v2 5/5] arm64: boot: dts: qcom: sdm845: Remove passive trip points for thermal zones 0-7 Thara Gopinath
2021-06-24 16:51 ` Matthias Kaehlcke
2021-06-25 15:44 ` Thara Gopinath
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=YNTFdCPU2saMCT/y@google.com \
--to=mka@chromium.org \
--cc=agross@kernel.org \
--cc=bjorn.andersson@linaro.org \
--cc=daniel.lezcano@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=rjw@rjwysocki.net \
--cc=robh+dt@kernel.org \
--cc=rui.zhang@intel.com \
--cc=thara.gopinath@linaro.org \
--cc=viresh.kumar@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).