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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id f61sm1549731otb.79.2021.07.09.20.11.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 20:11:41 -0700 (PDT) Date: Fri, 9 Jul 2021 22:11:39 -0500 From: Bjorn Andersson To: quic_vamslank@quicinc.com Cc: agross@kernel.org, robh+dt@kernel.org, linus.walleij@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, manivannan.sadhasivam@linaro.org Subject: Re: [PATCH 2/2] ARM: dts: qcom: Add SDX65 platform and MTP board support Message-ID: References: <20210709200506.20046-1-quic_vamslank@quicinc.com> <20210709200506.20046-3-quic_vamslank@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210709200506.20046-3-quic_vamslank@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri 09 Jul 15:05 CDT 2021, quic_vamslank@quicinc.com wrote: > From: Vamsi krishna Lanka > > Add basic devicetree support for SDX65 platform and MTP board from > Qualcomm. The SDX65 platform features an ARM Cortex A7 CPU which forms > the Application Processor Sub System (APSS) along with standard Qualcomm > peripherals like GCC, TLMM, BLSP, QPIC, and BAM etc... Also, there > exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem > etc.. > > This commit adds basic devicetree support that includes GCC, RPMh clock, INTC > and Debug UART. > > Signed-off-by: Vamsi Krishna Lanka > --- > arch/arm/boot/dts/Makefile | 3 +- > arch/arm/boot/dts/qcom-sdx65-mtp.dts | 25 ++++ > arch/arm/boot/dts/qcom-sdx65.dtsi | 215 +++++++++++++++++++++++++++ > 3 files changed, 242 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/boot/dts/qcom-sdx65-mtp.dts > create mode 100644 arch/arm/boot/dts/qcom-sdx65.dtsi > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 8e5d4ab4e75e..1e3f01496cb3 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -929,7 +929,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \ > qcom-msm8974-sony-xperia-castor.dtb \ > qcom-msm8974-sony-xperia-honami.dtb \ > qcom-mdm9615-wp8548-mangoh-green.dtb \ > - qcom-sdx55-mtp.dtb > + qcom-sdx55-mtp.dtb \ > + qcom-sdx65-mtp.dtb > dtb-$(CONFIG_ARCH_RDA) += \ > rda8810pl-orangepi-2g-iot.dtb \ > rda8810pl-orangepi-i96.dtb > diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts > new file mode 100644 > index 000000000000..59457da8e5f1 > --- /dev/null > +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts > @@ -0,0 +1,25 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > +/dts-v1/; > + > +#include "qcom-sdx65.dtsi" > + > +/ { > + model = "Qualcomm Technologies, Inc. SDX65 MTP"; > + compatible = "qcom,sdx65-mtp", "qcom,sdx65"; > + qcom,board-id = <0x2010008 0x302>; > + > + aliases { > + serial0 = &blsp1_uart3; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > + > +&blsp1_uart3 { > + status = "ok"; > +}; > diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi > new file mode 100644 > index 000000000000..4b5e7248c34d > --- /dev/null > +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi > @@ -0,0 +1,215 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * SDX65 SoC device tree source > + * > + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. > + * > + */ > + > +#include > +#include > +#include > +#include > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>; > + interrupt-parent = <&intc>; > + > + memory { > + device_type = "memory"; > + reg = <0 0>; > + }; > + > + clocks { > + xo_board: xo-board { > + compatible = "fixed-clock"; > + clock-frequency = <76800000>; > + clock-output-names = "xo_board"; > + #clock-cells = <0>; > + }; > + > + sleep_clk: sleep-clk { > + compatible = "fixed-clock"; > + clock-frequency = <32764>; > + clock-output-names = "sleep_clk"; > + #clock-cells = <0>; > + }; > + > + pcie_pipe_clk: pcie-0-pipe-clk { Rather than defining a dummy node to have something to provide in &gcc you can leave this as just 0 in the clocks property in &gcc until you introduce the PHY. > + compatible = "fixed-clock"; > + clock-frequency = <1000>; > + clock-output-names = "pcie_pipe_clk"; > + #clock-cells = <0>; > + }; > + > + usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk { Ditto. > + compatible = "fixed-clock"; > + clock-frequency = <1000>; > + clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk"; > + #clock-cells = <0>; > + }; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0x0>; > + enable-method = "psci"; > + }; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + soc: soc { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + compatible = "simple-bus"; > + > + gcc: clock-controller@100000 { > + compatible = "qcom,gcc-sdx65"; > + reg = <0x100000 0x1f7400>; Please pad the address to 8 digits, sto make it easier for me to keep these sorted by address as we move forward. > + reg-name = "cc_base"; We typically don't use a name for the single memory region for &gcc. I haven't looked at your gcc patch yet, but I think you should drop this. Regards, Bjorn > + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, > + <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; > + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", > + "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + blsp1_uart3: serial@831000 { > + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; > + reg = <0x00831000 0x200>; > + interrupts = ; > + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; > + clock-names = "core", "iface"; > + status = "disabled"; > + }; > + > + pdc: interrupt-controller@b210000 { > + compatible = "qcom,sdx65-pdc", "qcom,pdc"; > + reg = <0xb210000 0x10000>; > + qcom,pdc-ranges = <0 147 52>, <52 266 32>; > + #interrupt-cells = <2>; > + interrupt-parent = <&intc>; > + interrupt-controller; > + }; > + > + intc: interrupt-controller@17800000 { > + compatible = "qcom,msm-qgic2"; > + interrupt-controller; > + interrupt-parent = <&intc>; > + #interrupt-cells = <3>; > + reg = <0x17800000 0x1000>, > + <0x17802000 0x1000>; > + }; > + > + timer@17820000 { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + compatible = "arm,armv7-timer-mem"; > + reg = <0x17820000 0x1000>; > + clock-frequency = <19200000>; > + > + frame@17821000 { > + frame-number = <0>; > + interrupts = , > + ; > + reg = <0x17821000 0x1000>, > + <0x17822000 0x1000>; > + }; > + > + frame@17823000 { > + frame-number = <1>; > + interrupts = ; > + reg = <0x17823000 0x1000>; > + status = "disabled"; > + }; > + > + frame@17824000 { > + frame-number = <2>; > + interrupts = ; > + reg = <0x17824000 0x1000>; > + status = "disabled"; > + }; > + > + frame@17825000 { > + frame-number = <3>; > + interrupts = ; > + reg = <0x17825000 0x1000>; > + status = "disabled"; > + }; > + > + frame@17826000 { > + frame-number = <4>; > + interrupts = ; > + reg = <0x17826000 0x1000>; > + status = "disabled"; > + }; > + > + frame@17827000 { > + frame-number = <5>; > + interrupts = ; > + reg = <0x17827000 0x1000>; > + status = "disabled"; > + }; > + > + frame@17828000 { > + frame-number = <6>; > + interrupts = ; > + reg = <0x17828000 0x1000>; > + status = "disabled"; > + }; > + > + frame@17829000 { > + frame-number = <7>; > + interrupts = ; > + reg = <0x17829000 0x1000>; > + status = "disabled"; > + }; > + }; > + > + apps_rsc: rsc@17830000 { > + label = "apps_rsc"; > + compatible = "qcom,rpmh-rsc"; > + reg = <0x17830000 0x10000>, > + <0x17840000 0x10000>; > + reg-names = "drv-0", "drv-1"; > + interrupts = , > + ; > + qcom,tcs-offset = <0xd00>; > + qcom,drv-id = <1>; > + qcom,tcs-config = , > + , > + , > + ; > + > + rpmhcc: clock-controller@1 { > + compatible = "qcom,sdx65-rpmh-clk"; > + #clock-cells = <1>; > + clock-names = "xo"; > + clocks = <&xo_board>; > + }; > + }; > + }; > + > + timer { > + compatible = "arm,armv7-timer"; > + interrupts = <1 13 0xf08>, > + <1 12 0xf08>, > + <1 10 0xf08>, > + <1 11 0xf08>; > + clock-frequency = <19200000>; > + }; > +}; > -- > 2.32.0 >