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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id q63sm404390ooq.4.2021.07.16.13.18.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Jul 2021 13:18:59 -0700 (PDT) Date: Fri, 16 Jul 2021 15:18:56 -0500 From: Bjorn Andersson To: Rajendra Nayak Cc: ulf.hansson@linaro.org, viresh.kumar@linaro.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, swboyd@chromium.org, rojay@codeaurora.org, stephan@gerhold.net Subject: Re: [PATCH v4 2/2] arm64: dts: sc7180: Add required-opps for i2c Message-ID: References: <1626429658-18961-1-git-send-email-rnayak@codeaurora.org> <1626429658-18961-3-git-send-email-rnayak@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1626429658-18961-3-git-send-email-rnayak@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri 16 Jul 05:00 CDT 2021, Rajendra Nayak wrote: > qup-i2c devices on sc7180 are clocked with a fixed clock (19.2 MHz) > Though qup-i2c does not support DVFS, it still needs to vote for a > performance state on 'CX' to satisfy the 19.2 Mhz clock frequency > requirement. > Sounds good, but... > Use 'required-opps' to pass this information from > device tree, and also add the power-domains property to specify > the CX power-domain. > ..is the required-opps really needed with my rpmhpd patch in place? Regards, Bjorn > Signed-off-by: Rajendra Nayak > --- > arch/arm64/boot/dts/qcom/sc7180.dtsi | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi > index a5d58eb..cd30185 100644 > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > @@ -785,8 +785,10 @@ > <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, > <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > interconnect-names = "qup-core", "qup-config", > "qup-memory"; > + power-domains = <&rpmhpd SC7180_CX>; > + required-opps = <&rpmhpd_opp_low_svs>; > status = "disabled"; > }; > > spi0: spi@880000 { > @@ -837,8 +839,10 @@ > <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, > <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > interconnect-names = "qup-core", "qup-config", > "qup-memory"; > + power-domains = <&rpmhpd SC7180_CX>; > + required-opps = <&rpmhpd_opp_low_svs>; > status = "disabled"; > }; > > spi1: spi@884000 { > @@ -889,8 +893,10 @@ > <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, > <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > interconnect-names = "qup-core", "qup-config", > "qup-memory"; > + power-domains = <&rpmhpd SC7180_CX>; > + required-opps = <&rpmhpd_opp_low_svs>; > status = "disabled"; > }; > > uart2: serial@888000 { > @@ -923,8 +929,10 @@ > <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, > <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > interconnect-names = "qup-core", "qup-config", > "qup-memory"; > + power-domains = <&rpmhpd SC7180_CX>; > + required-opps = <&rpmhpd_opp_low_svs>; > status = "disabled"; > }; > > spi3: spi@88c000 { > @@ -975,8 +983,10 @@ > <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, > <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > interconnect-names = "qup-core", "qup-config", > "qup-memory"; > + power-domains = <&rpmhpd SC7180_CX>; > + required-opps = <&rpmhpd_opp_low_svs>; > status = "disabled"; > }; > > uart4: serial@890000 { > @@ -1009,8 +1019,10 @@ > <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, > <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > interconnect-names = "qup-core", "qup-config", > "qup-memory"; > + power-domains = <&rpmhpd SC7180_CX>; > + required-opps = <&rpmhpd_opp_low_svs>; > status = "disabled"; > }; > > spi5: spi@894000 { > @@ -1074,8 +1086,10 @@ > <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, > <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > interconnect-names = "qup-core", "qup-config", > "qup-memory"; > + power-domains = <&rpmhpd SC7180_CX>; > + required-opps = <&rpmhpd_opp_low_svs>; > status = "disabled"; > }; > > spi6: spi@a80000 { > @@ -1126,8 +1140,10 @@ > <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, > <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > interconnect-names = "qup-core", "qup-config", > "qup-memory"; > + power-domains = <&rpmhpd SC7180_CX>; > + required-opps = <&rpmhpd_opp_low_svs>; > status = "disabled"; > }; > > uart7: serial@a84000 { > @@ -1160,8 +1176,10 @@ > <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, > <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > interconnect-names = "qup-core", "qup-config", > "qup-memory"; > + power-domains = <&rpmhpd SC7180_CX>; > + required-opps = <&rpmhpd_opp_low_svs>; > status = "disabled"; > }; > > spi8: spi@a88000 { > @@ -1212,8 +1230,10 @@ > <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, > <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > interconnect-names = "qup-core", "qup-config", > "qup-memory"; > + power-domains = <&rpmhpd SC7180_CX>; > + required-opps = <&rpmhpd_opp_low_svs>; > status = "disabled"; > }; > > uart9: serial@a8c000 { > @@ -1246,8 +1266,10 @@ > <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, > <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > interconnect-names = "qup-core", "qup-config", > "qup-memory"; > + power-domains = <&rpmhpd SC7180_CX>; > + required-opps = <&rpmhpd_opp_low_svs>; > status = "disabled"; > }; > > spi10: spi@a90000 { > @@ -1298,8 +1320,10 @@ > <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, > <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > interconnect-names = "qup-core", "qup-config", > "qup-memory"; > + power-domains = <&rpmhpd SC7180_CX>; > + required-opps = <&rpmhpd_opp_low_svs>; > status = "disabled"; > }; > > spi11: spi@a94000 { > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation >