From: Matthias Kaehlcke <mka@chromium.org>
To: Sibi Sankar <sibis@codeaurora.org>
Cc: bjorn.andersson@linaro.org, tdas@codeaurora.org,
agross@kernel.org, robh+dt@kernel.org,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, stable@vger.kernel.org
Subject: Re: [PATCH] arm64: dts: qcom: sc7280: Fixup cpufreq domain info for cpu7
Date: Tue, 20 Jul 2021 10:50:31 -0700 [thread overview]
Message-ID: <YPcM5w60c5s+mZ4Y@google.com> (raw)
In-Reply-To: <1626800953-613-1-git-send-email-sibis@codeaurora.org>
On Tue, Jul 20, 2021 at 10:39:13PM +0530, Sibi Sankar wrote:
> The SC7280 SoC supports a 4-Silver/3-Gold/1-Gold+ configuration and hence
> the cpu7 node should point to cpufreq domain 2 instead.
>
> Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node")
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> Cc: stable@vger.kernel.org
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index a8c274ad74c4..188c5768a55a 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -200,7 +200,7 @@
> &BIG_CPU_SLEEP_1
> &CLUSTER_SLEEP_0>;
> next-level-cache = <&L2_700>;
> - qcom,freq-domain = <&cpufreq_hw 1>;
> + qcom,freq-domain = <&cpufreq_hw 2>;
> #cooling-cells = <2>;
> L2_700: l2-cache {
> compatible = "cache";
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
next prev parent reply other threads:[~2021-07-20 17:51 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-20 17:09 [PATCH] arm64: dts: qcom: sc7280: Fixup cpufreq domain info for cpu7 Sibi Sankar
2021-07-20 17:50 ` Matthias Kaehlcke [this message]
2021-07-21 22:50 ` Stephen Boyd
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