Re: [PATCH v9 01/11] phy: HiSilicon: Add driver for Kirin 970 PCIe PHY

[Vinod Koul <vkoul@kernel.org>]

On 04-08-21, 18:02, Mauro Carvalho Chehab wrote:

> +/* define ie,oe cfg */
> +#define IO_IE_EN_HARD_BYPASS         (0x1 << 27)
> +#define IO_OE_EN_HARD_BYPASS         (0x1 << 11)
> +#define IO_HARD_CTRL_DEBOUNCE_BYPASS (0x1 << 10)
> +#define IO_OE_GT_MODE                (0x2 << 7)
> +#define DEBOUNCE_WAITCFG_IN          (0xf << 20)
> +#define DEBOUNCE_WAITCFG_OUT         (0xf << 13)

Why not use BIT() or GENMASK for these?

> +/* Registers in PCIePHY */
> +static inline void hi3670_apb_phy_writel(struct hi3670_pcie_phy *phy,
> +					 u32 val, u32 reg)
> +{
> +	writel(val, phy->base + 0x40000 + reg);

magic 0x40000?

> +}
> +
> +static inline u32 hi3670_apb_phy_readl(struct hi3670_pcie_phy *phy, u32 reg)
> +{
> +	return readl(phy->base + 0x40000 + reg);
> +}
> +
> +static inline void kirin_apb_natural_phy_writel(struct hi3670_pcie_phy *phy,
> +						u32 val, u32 reg)
> +{
> +	writel(val, phy->base + reg * 4);

why * 4 ..?

> +static void hi3670_pcie_set_eyeparam(struct hi3670_pcie_phy *phy)
> +{
> +	u32 val;
> +
> +	val = kirin_apb_natural_phy_readl(phy, RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1);
> +
> +	if (phy->eye_param[1] != EYEPARAM_NOCFG) {
> +		val &= (~0xf00);
> +		val |= (phy->eye_param[1] << 8) | (0x1 << 12);
> +	}

again too many magic numbers, Do check FIELD_GET/PREP macros for these?
-- 
~Vinod