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[35.185.214.157]) by smtp.gmail.com with ESMTPSA id f31sm1131486pgm.1.2021.07.28.16.44.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jul 2021 16:44:44 -0700 (PDT) Date: Wed, 28 Jul 2021 23:44:41 +0000 From: Sean Christopherson To: Zeng Guang Cc: Paolo Bonzini , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, Dave Hansen , Tony Luck , Kan Liang , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , Kim Phillips , Jarkko Sakkinen , Jethro Beekman , Kai Huang , x86@kernel.org, linux-kernel@vger.kernel.org, Robert Hu , Gao Chao , Robert Hoo Subject: Re: [PATCH 1/6] x86/feat_ctl: Add new VMX feature, Tertiary VM-Execution control Message-ID: References: <20210716064808.14757-1-guang.zeng@intel.com> <20210716064808.14757-2-guang.zeng@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210716064808.14757-2-guang.zeng@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jul 16, 2021, Zeng Guang wrote: > From: Robert Hoo > > New VMX capability MSR IA32_VMX_PROCBASED_CTLS3 conresponse to this new > VM-Execution control field. And it is 64bit allow-1 semantics, not like > previous capability MSRs 32bit allow-0 and 32bit allow-1. So with Tertiary > VM-Execution control field introduced, 2 vmx_feature leaves are introduced, > TERTIARY_CTLS_LOW and TERTIARY_CTLS_HIGH. ... > /* > * Note: If the comment begins with a quoted string, that string is used > @@ -43,6 +43,7 @@ > #define VMX_FEATURE_RDTSC_EXITING ( 1*32+ 12) /* "" VM-Exit on RDTSC */ > #define VMX_FEATURE_CR3_LOAD_EXITING ( 1*32+ 15) /* "" VM-Exit on writes to CR3 */ > #define VMX_FEATURE_CR3_STORE_EXITING ( 1*32+ 16) /* "" VM-Exit on reads from CR3 */ > +#define VMX_FEATURE_TER_CONTROLS (1*32 + 17) /* "" Enable Tertiary VM-Execution Controls */ Maybe spell out TERTIARY? SEC_CONTROLS is at least somewhat guessable, I doubt TERTIARY is the first thing that comes to mind for most people when seeing "TER" :-) > #define VMX_FEATURE_CR8_LOAD_EXITING ( 1*32+ 19) /* "" VM-Exit on writes to CR8 */ > #define VMX_FEATURE_CR8_STORE_EXITING ( 1*32+ 20) /* "" VM-Exit on reads from CR8 */ > #define VMX_FEATURE_VIRTUAL_TPR ( 1*32+ 21) /* "vtpr" TPR virtualization, a.k.a. TPR shadow */ > diff --git a/arch/x86/kernel/cpu/feat_ctl.c b/arch/x86/kernel/cpu/feat_ctl.c > index da696eb4821a..2e0272d127e4 100644 > --- a/arch/x86/kernel/cpu/feat_ctl.c > +++ b/arch/x86/kernel/cpu/feat_ctl.c > @@ -15,6 +15,8 @@ enum vmx_feature_leafs { > MISC_FEATURES = 0, > PRIMARY_CTLS, > SECONDARY_CTLS, > + TERTIARY_CTLS_LOW, > + TERTIARY_CTLS_HIGH, > NR_VMX_FEATURE_WORDS, > }; > > @@ -42,6 +44,13 @@ static void init_vmx_capabilities(struct cpuinfo_x86 *c) > rdmsr_safe(MSR_IA32_VMX_PROCBASED_CTLS2, &ign, &supported); > c->vmx_capability[SECONDARY_CTLS] = supported; > > + /* > + * For tertiary execution controls MSR, it's actually a 64bit allowed-1. > + */ > + rdmsr_safe(MSR_IA32_VMX_PROCBASED_CTLS3, &ign, &supported); > + c->vmx_capability[TERTIARY_CTLS_LOW] = ign; > + c->vmx_capability[TERTIARY_CTLS_HIGH] = supported; Assuming only the lower 32 bits are going to be used for the near future (next few years), what about defining just TERTIARY_CTLS_LOW and then doing: /* * Tertiary controls are 64-bit allowed-1, so unlikely other MSRs, the * upper bits are ignored (because they're not used, yet...). */ rdmsr_safe(MSR_IA32_VMX_PROCBASED_CTLS3, &supported, &ign); c->vmx_capability[TERTIARY_CTLS_LOW] = supported; I.e. punt the ugliness issue down the road a few years. > + > rdmsr(MSR_IA32_VMX_PINBASED_CTLS, ign, supported); > rdmsr_safe(MSR_IA32_VMX_VMFUNC, &ign, &funcs); > > -- > 2.25.1 >