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From: Rob Herring <robh@kernel.org>
To: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Cc: Linuxarm <linuxarm@huawei.com>,
	mauro.chehab@huawei.com, Binghui Wang <wangbinghui@hisilicon.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Xiaowei Song <songxiaowei@hisilicon.com>,
	devicetree@vger.kernel.org,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	PCI <linux-pci@vger.kernel.org>
Subject: Re: [PATCH 3/5] dt-bindings: PCI: kirin: Add support for Kirin970
Date: Mon, 2 Aug 2021 16:50:53 -0600	[thread overview]
Message-ID: <YQh2zcFSKW+qucAG@robh.at.kernel.org> (raw)
In-Reply-To: <20210729210337.6fc9a92c@coco.lan>

On Thu, Jul 29, 2021 at 09:03:37PM +0200, Mauro Carvalho Chehab wrote:
> Em Thu, 29 Jul 2021 09:20:15 -0600
> Rob Herring <robh@kernel.org> escreveu:
> 
> > On Thu, Jul 29, 2021 at 5:56 AM Mauro Carvalho Chehab
> > <mchehab+huawei@kernel.org> wrote:
> > >
> > > Add a new compatible, plus the new bindings needed by
> > > HiKey970 board.
> > >
> > > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
> > > ---
> > >  .../bindings/pci/hisilicon,kirin-pcie.yaml    | 61 ++++++++++++++++++-
> > >  1 file changed, 60 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
> > > index 90cab09e8d4b..bb0c3a081d68 100644
> > > --- a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
> > > +++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
> > > @@ -24,11 +24,13 @@ properties:
> > >      contains:
> > >        enum:
> > >          - hisilicon,kirin960-pcie
> > > +        - hisilicon,kirin970-pcie
> > >
> > >    reg:
> > >      description: |
> > >        Should contain dbi, apb, config registers location and length.
> > > -      For HiKey960, it should also contain phy.
> > > +      For HiKey960, it should also contain phy. All other devices
> > > +      should use a separate phy driver.
> > >      minItems: 3
> > >      maxItems: 4
> > >
> > > @@ -47,6 +49,7 @@ examples:
> > >    - |
> > >      #include <dt-bindings/interrupt-controller/arm-gic.h>
> > >      #include <dt-bindings/clock/hi3660-clock.h>
> > > +    #include <dt-bindings/clock/hi3670-clock.h>
> > >
> > >      soc {
> > >        #address-cells = <2>;
> > > @@ -83,4 +86,60 @@ examples:
> > >          clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy",
> > >                        "pcie_apb_sys", "pcie_aclk";
> > >        };
> > > +
> > > +      pcie@f5000000 {
> > > +        compatible = "hisilicon,kirin970-pcie";
> > > +        reg = <0x0 0xf4000000 0x0 0x1000000>,
> > > +              <0x0 0xfc180000 0x0 0x1000>,
> > > +              <0x0 0xf5000000 0x0 0x2000>;
> > > +        reg-names = "dbi", "apb", "config";
> > > +        bus-range = <0x0  0x1>;
> > > +        msi-parent = <&its_pcie>;
> > > +        #address-cells = <3>;
> > > +        #size-cells = <2>;
> > > +        device_type = "pci";
> > > +        phys = <&pcie_phy>;
> > > +        ranges = <0x02000000 0x0 0x00000000
> > > +                  0x0 0xf6000000
> > > +                  0x0 0x02000000>;
> > > +        num-lanes = <1>;
> > > +        #interrupt-cells = <1>;
> > > +        interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
> > > +        interrupt-names = "msi";
> > > +        interrupt-map-mask = <0 0 0 7>;
> > > +        interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
> > > +                        <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> > > +                        <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
> > > +                        <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
> > > +        pcie@4,0 { // Lane 4: M.2
> > > +          reg = <0 0 0 0 0>;
> > > +          compatible = "pciclass,0604";
> > > +          device_type = "pci";
> > > +          reset-gpios = <&gpio7 1 0>;
> > > +          clkreq-gpios = <&gpio27 3 0 >;  
> > 
> > Looking at the schematics some more, this is not right. CLKREQ# is an
> > input from the device, and they are not connected to any GPIO (just
> > pulled high) on hikey970. These GPIOs are simply clock enables and
> > very much specific to hikey. So I'd call this 'hisilicon,clken-gpios'
> > and you can just stick them in the host bridge node.
> > 
> 
> Ok. If I understood your review, the schema will then be:
> 
>       pcie@f4000000 {
>         compatible = "hisilicon,kirin970-pcie";
>         reg = <0x0 0xf4000000 0x0 0x1000000>,
>               <0x0 0xfc180000 0x0 0x1000>,
>               <0x0 0xf5000000 0x0 0x2000>;
>         reg-names = "dbi", "apb", "config";
>         bus-range = <0x0  0x1>;
>         msi-parent = <&its_pcie>;
>         #address-cells = <3>;
>         #size-cells = <2>;
>         device_type = "pci";
>         phys = <&pcie_phy>;
>         ranges = <0x02000000 0x0 0x00000000
>                   0x0 0xf6000000
>                   0x0 0x02000000>;
>         num-lanes = <1>;
>         #interrupt-cells = <1>;
>         interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
>         interrupt-names = "msi";
>         interrupt-map-mask = <0 0 0 7>;
>         interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
>                         <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
>                         <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
>                         <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
>         reset-gpios = <&gpio7 0 0>;
> 
>         pcie@0 { // Lane 0: upstream
>           reg = <0 0 0 0 0>;
>           compatible = "pciclass,0604";
>           device_type = "pci";
>           #address-cells = <3>;
>           #size-cells = <2>;
>           hisilicon,clken-gpios = <&gpio27 3 0 >, <&gpio17 0 0 >, <&gpio20 6 0 >;

Up one more level.

>           ranges;
> 
>           pcie@1,0 { // Lane 4: M.2
>             reg = <0x800 0 0 0 0>;
>             compatible = "pciclass,0604";
>             device_type = "pci";
>             reset-gpios = <&gpio3 1 0>;
>             #address-cells = <3>;
>             #size-cells = <2>;
>             ranges;
>           };
> 
>           pcie@5,0 { // Lane 5: Mini PCIe
>             reg = <0x2800 0 0 0 0>;
>             compatible = "pciclass,0604";
>             device_type = "pci";
>             reset-gpios = <&gpio27 4 0 >;
>             #address-cells = <3>;
>             #size-cells = <2>;
>             ranges;
>           };
> 
>           pcie@7,0 { // Lane 7: Ethernet

Port 7 is lane 6 and Port 9 is lane 7. So I think it should be 'Lane 6'. 

>             reg = <0x3800 0 0 0 0>;
>             compatible = "pciclass,0604";
>             device_type = "pci";
>             reset-gpios = <&gpio25 2 0 >;
>             #address-cells = <3>;
>             #size-cells = <2>;
>             ranges;
>           };
>         };
>       };
>     };
> 
> Right?
> 
> After updating the dt-schema from your git tree, the above doesn't 
> generate warnings anymore.
> 
> Thanks,
> Mauro
> 

  reply	other threads:[~2021-08-02 22:51 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-29 11:56 [PATCH 0/5] DT schema changes for HiKey970 PCIe hardware to work Mauro Carvalho Chehab
2021-07-29 11:56 ` [PATCH 1/5] dt-bindings: PCI: kirin: Fix compatible string Mauro Carvalho Chehab
2021-07-29 11:56 ` [PATCH 2/5] dt-bindings: PCI: kirin: convert kirin-pcie.txt to yaml Mauro Carvalho Chehab
2021-07-29 11:56 ` [PATCH 3/5] dt-bindings: PCI: kirin: Add support for Kirin970 Mauro Carvalho Chehab
2021-07-29 14:50   ` Rob Herring
2021-07-29 15:20   ` Rob Herring
2021-07-29 19:03     ` Mauro Carvalho Chehab
2021-08-02 22:50       ` Rob Herring [this message]
2021-08-03  4:33         ` Mauro Carvalho Chehab
2021-07-29 11:56 ` [PATCH 4/5] dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY Mauro Carvalho Chehab
2021-07-29 11:56 ` [PATCH 5/5] arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller hardware Mauro Carvalho Chehab
2021-07-29 17:20 ` [PATCH 0/5] DT schema changes for HiKey970 PCIe hardware to work Rob Herring

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