From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: quic_vamslank@quicinc.com
Cc: agross@kernel.org, linus.walleij@linaro.org,
manivannan.sadhasivam@linaro.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org
Subject: Re: [PATCH v2 1/2] dt-bindings: pinctrl: qcom: Add SDX65 pinctrl bindings
Date: Wed, 18 Aug 2021 22:03:02 -0500 [thread overview]
Message-ID: <YR3J5jHr2CTTU92D@builder.lan> (raw)
In-Reply-To: <341f8af967fb0c699996a8f73d34c2b8bd0789cc.1626987605.git.quic_vamslank@quicinc.com>
On Thu 22 Jul 16:18 CDT 2021, quic_vamslank@quicinc.com wrote:
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml
[..]
> +'$defs':
> + qcom-sdx65-tlmm-state:
> + type: object
> + description:
> + Pinctrl node's client devices use subnodes for desired pin configuration.
> + Client device subnodes use below standard properties.
> + $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
> +
> + properties:
> + pins:
> + description:
> + List of gpio pins affected by the properties specified in this subnode.
> + items:
> + oneOf:
> + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$"
The last part doesn't seem right and this gives us the following
possible values gpio0-9, gpio10-99, gpio100-106 and gpio110-116.
I think the correct pattern would be:
"^gpio([0-9]|[1-9][0-9]|10[0-9])$"
[..]
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-controller
> + - '#interrupt-cells'
> + - gpio-controller
> + - '#gpio-cells'
> + - gpio-ranges
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + tlmm: pinctrl@f100000{
Please include a space between the unit address and '{'.
> + compatible = "qcom,sdx65-tlmm";
> + reg = <0x03000000 0xdc2000>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&tlmm 0 0 109>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
> +
> + serial-pins {
> + pins = "gpio8", "gpio9";
> + function = "blsp_uart3";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + uart-w-subnodes-state {
This line is indented with tabs, the rest with spaces.
With those changes this looks really good.
Thanks,
Bjorn
next prev parent reply other threads:[~2021-08-19 3:03 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-22 21:18 [PATCH v2 0/2] Add pinctrl support for SDX65 quic_vamslank
2021-07-22 21:18 ` [PATCH v2 1/2] dt-bindings: pinctrl: qcom: Add SDX65 pinctrl bindings quic_vamslank
2021-08-19 3:03 ` Bjorn Andersson [this message]
2021-07-22 21:18 ` [PATCH v2 2/2] pinctrl: qcom: Add SDX65 pincontrol driver quic_vamslank
2021-08-19 3:09 ` Bjorn Andersson
2021-07-30 10:02 ` [PATCH v2 0/2] Add pinctrl support for SDX65 Linus Walleij
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