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From: Vinod Koul <>
To: Iskren Chernev <>
Cc: Bjorn Andersson <>,
	Andy Gross <>,
	Kishon Vijay Abraham I <>,
	Manu Gautam <>,
	Rob Herring <>,,,,,,
Subject: Re: [PATCH v1 2/2] phy: qcom-qmp: Add support for SM6115 UFS phy
Date: Mon, 9 Aug 2021 10:18:11 +0530	[thread overview]
Message-ID: <YRCzi9tXsUVi5kHS@matsya> (raw)
In-Reply-To: <>

On 06-08-21, 19:09, Iskren Chernev wrote:
> On 8/6/21 3:57 PM, Vinod Koul wrote:
> > On 05-08-21, 12:17, Iskren Chernev wrote:

> > why are these registers 660 specific and not V3 like we have for
> > other generations..? Quick looks with V3 regs tells me that seem
> > similar....
> >
> Well, I looked at them for a long time and the only thing that is similar
> are the first few QSERDES registers from COM_ATB_SEL1=0x000 to
> COM_BIAS_EN_CLKBUFLR_EN=0x034. Everything else is different. So I can re-use

Is the offset different? I thought all Vn registers across chips do have
same offsets..

> the V3 for the similar regs, but they are 10%, so I figured instead of combing
> through all of the sequences to save 10% of the constants and make it slightly
> less readable just use new constants.
> Let me know if I should reuse the 14 regs from V3.

reuse yes, but would like to understand more why offsets are different,

Can you point me to downstream code reference for this?


  reply	other threads:[~2021-08-09  4:48 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-05  9:17 [PATCH v1 0/2] Add UFS PHY support for SM6115/4250 Iskren Chernev
2021-08-05  9:17 ` [PATCH v1 1/2] dt-bindings: phy: qcom,qmp: Add SM6115 UFS PHY bindings Iskren Chernev
2021-08-13 18:38   ` Rob Herring
2021-08-05  9:17 ` [PATCH v1 2/2] phy: qcom-qmp: Add support for SM6115 UFS phy Iskren Chernev
2021-08-06 12:57   ` Vinod Koul
2021-08-06 16:09     ` Iskren Chernev
2021-08-09  4:48       ` Vinod Koul [this message]
2021-08-09 14:20         ` Iskren Chernev

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