From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAD19C432BE for ; Wed, 11 Aug 2021 17:59:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8E8F560FE6 for ; Wed, 11 Aug 2021 17:59:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229863AbhHKSAC (ORCPT ); Wed, 11 Aug 2021 14:00:02 -0400 Received: from perceval.ideasonboard.com ([213.167.242.64]:35812 "EHLO perceval.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229473AbhHKSAB (ORCPT ); Wed, 11 Aug 2021 14:00:01 -0400 Received: from pendragon.ideasonboard.com (62-78-145-57.bb.dnainternet.fi [62.78.145.57]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 67DDFEE; Wed, 11 Aug 2021 19:59:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1628704775; bh=BMsdi7My1VYTMrplXoEmSnQucwP+J/DbPd0dzrnNBsM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=IHxA1AMILWKIHji8vmE4Bnzr2zmoUHodN+zQtrlMsQXc2KnZ8/0jXPdvhcRyMK9Y0 biqdsyNn4CTwpBw/Wf+8yaT/O4PgR/8Akw0izPsfspboLK84s9qqEGgnTlP3HzMB7o 2CsHjgO66+Hz0AV3k68PC9sB+etZaCQAptgb114Q= Date: Wed, 11 Aug 2021 20:59:32 +0300 From: Laurent Pinchart To: Yunfei Dong Cc: Alexandre Courbot , Hans Verkuil , Tzung-Bi Shih , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa , Hsin-Yi Wang , Fritz Koenig , Irui Wang , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, srv_heupstream@mediatek.com, linux-mediatek@lists.infradead.org, Project_Global_Chrome_Upstream_Group@mediatek.com, George Sun Subject: Re: [PATCH v5, 13/15] dt-bindings: media: mtk-vcodec: Adds decoder dt-bindings for mt8192 Message-ID: References: <20210811025801.21597-1-yunfei.dong@mediatek.com> <20210811025801.21597-14-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20210811025801.21597-14-yunfei.dong@mediatek.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Yunfei, Thank you for the patch. On Wed, Aug 11, 2021 at 10:57:59AM +0800, Yunfei Dong wrote: > Adds decoder dt-bindings for mt8192. > > Signed-off-by: Yunfei Dong > --- > v5: no changes > > This patch depends on "Mediatek MT8192 clock support"[1]. > > The definition of decoder clocks are in mt8192-clk.h, need to include them in case of build fail [1]. > > [1]https://patchwork.kernel.org/project/linux-mediatek/list/?series=511175 > --- > .../media/mediatek,vcodec-comp-decoder.yaml | 172 ++++++++++++++++++ > 1 file changed, 172 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml > > diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml > new file mode 100644 > index 000000000000..083c89933917 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml > @@ -0,0 +1,172 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/iommu/mediatek,vcodec-comp-decoder.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Mediatek Video Decode Accelerator With Component > + > +maintainers: > + - Yunfei Dong > + > +description: |+ > + Mediatek Video Decode is the video decode hardware present in Mediatek > + SoCs which supports high resolution decoding functionalities. Required > + master and component node. This should explain how the three IP cores relate to each other. > + > +properties: > + compatible: > + oneOf: > + - enum: > + - mediatek,mt8192-vcodec-dec # for lat hardware > + - mediatek,mtk-vcodec-lat # for core hardware > + - mediatek,mtk-vcodec-core > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 5 > + > + clock-names: > + items: > + - const: vdec-sel > + - const: vdec-soc-vdec > + - const: vdec-soc-lat > + - const: vdec-vdec > + - const: vdec-top > + > + assigned-clocks: true > + > + assigned-clock-parents: true > + > + power-domains: > + maxItems: 1 > + > + iommus: > + minItems: 1 > + maxItems: 32 > + description: | > + List of the hardware port in respective IOMMU block for current Socs. > + Refer to bindings/iommu/mediatek,iommu.yaml. > + > + dma-ranges: > + maxItems: 1 > + description: | > + Describes the physical address space of IOMMU maps to memory. > + > + mediatek,scp: > + $ref: /schemas/types.yaml#/definitions/phandle > + maxItems: 1 > + description: > + Describes point to scp. > + > +required: > + - compatible > + - reg > + - iommus > + - dma-ranges > + > +allOf: > + - if: #master node > + properties: > + compatible: > + contains: > + enum: > + - mediatek,mt8192-vcodec-dec # for lat hardware > + > + then: > + required: > + - mediatek,scp > + > + - if: #component node > + properties: > + compatible: > + contains: > + enum: > + - mediatek,mtk-vcodec-lat # for core hardware > + - mediatek,mtk-vcodec-core > + > + then: > + required: > + - interrupts > + - clocks > + - clock-names > + - assigned-clocks > + - assigned-clock-parents > + - power-domains > + > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + #include > + > + vcodec_dec: vcodec_dec@16000000 { > + compatible = "mediatek,mt8192-vcodec-dec"; > + reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */ > + mediatek,scp = <&scp>; > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; > + }; > + > + vcodec_lat: vcodec_lat@0x16010000 { > + compatible = "mediatek,mtk-vcodec-lat"; > + reg = <0 0x16010000 0 0x800>; /* VDEC_MISC */ > + interrupts = ; > + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; > + clocks = <&topckgen CLK_TOP_VDEC_SEL>, > + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, > + <&vdecsys_soc CLK_VDEC_SOC_LAT>, > + <&vdecsys_soc CLK_VDEC_SOC_LARB1>, > + <&topckgen CLK_TOP_MAINPLL_D4>; > + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", > + "vdec-vdec", "vdec-top"; > + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; > + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; > + }; > + > + vcodec_core: vcodec_core@0x16025000 { > + compatible = "mediatek,mtk-vcodec-core"; > + reg = <0 0x16025000 0 0x1000>; /* VDEC_CORE_MISC */ > + interrupts = ; > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; > + clocks = <&topckgen CLK_TOP_VDEC_SEL>, > + <&vdecsys CLK_VDEC_VDEC>, > + <&vdecsys CLK_VDEC_LAT>, > + <&vdecsys CLK_VDEC_LARB1>, > + <&topckgen CLK_TOP_MAINPLL_D4>; > + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", > + "vdec-vdec", "vdec-top"; > + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; > + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; > + }; I'm a bit late in the game, reviewing v5 only, but I'm wondering if those IP cores need to be modelled in separate nodes. It would be much easier, from a software point of view, to have a single node, with multiple register ranges. Are some of those IP cores used in different SoCs, combined in different ways, that make a modular design better ? -- Regards, Laurent Pinchart