From: Rob Herring <robh@kernel.org>
To: Bhaskara Budiredla <bbudiredla@marvell.com>
Cc: will@kernel.org, mark.rutland@arm.com, sgoutham@marvell.com,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 2/2] dt-bindings: perf: Add YAML schemas for Marvell CN10K LLC-TAD pmu bindings
Date: Tue, 7 Sep 2021 13:24:02 -0500 [thread overview]
Message-ID: <YTeuQvMoFOeY0FeJ@robh.at.kernel.org> (raw)
In-Reply-To: <20210901150105.18863-3-bbudiredla@marvell.com>
On Wed, Sep 01, 2021 at 08:31:05PM +0530, Bhaskara Budiredla wrote:
> Add device tree bindings for Last-level-cache Tag-and-data
> (LLC-TAD) unit PMU for Marvell CN10K SoCs.
>
> Signed-off-by: Bhaskara Budiredla <bbudiredla@marvell.com>
> ---
> .../bindings/perf/marvell-cn10k-tad.yaml | 60 +++++++++++++++++++
marvell,cn10k-tad-pmu.yaml
> 1 file changed, 60 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml
>
> diff --git a/Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml b/Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml
> new file mode 100644
> index 000000000000..18e9499f2df8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml
> @@ -0,0 +1,60 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/perf/marvell-cn10k-tad.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Marvell CN10K LLC-TAD performance monitor
> +
> +maintainers:
> + - Bhaskara Budiredla <bbudiredla@marvell.com>
> +
> +description: |
> + The Tag-and-Data units (TADs) maintain coherence and contain CN10K
> + shared on-chip last level cache (LLC). The tad pmu measures the
> + performance of last-level cache. Each tad pmu supports up to eight
> + counters.
> +
> + The DT setup comprises of number of tad blocks, the sizes of pmu
> + regions, tad blocks and overall base address of the HW.
> +
> +properties:
> + compatible:
> + const: marvell,cn10k-tad-pmu
> +
> + tad-cnt:
> + maxItems: 1
> +
> + tad-page-size:
> + maxItems: 1
> +
> + tad-pmu-page-size:
> + maxItems: 1
These all need vendor prefix, a type, description, and any constraints.
> +
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - tad-cnt
> + - tad-page-size
> + - tad-pmu-page-size
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +
> + tad {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + tad_pmu@80000000 {
pmu@...
> + compatible = "marvell,cn10k-tad-pmu";
> + tad-cnt = <1>;
> + tad-page-size = <0x1000>;
> + tad-pmu-page-size = <0x1000>;
> + reg = <0x87e2 0x80000000 0x0 0x1000>;
> + };
> + };
> --
> 2.17.1
>
>
prev parent reply other threads:[~2021-09-07 18:24 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-01 15:01 [PATCH v4 0/2] drivers: perf: Add Marvell CN10K LLC-TAD pmu driver Bhaskara Budiredla
2021-09-01 15:01 ` [PATCH v4 1/2] drivers: perf: Add LLC-TAD perf counter support Bhaskara Budiredla
2021-09-01 15:01 ` [PATCH v4 2/2] dt-bindings: perf: Add YAML schemas for Marvell CN10K LLC-TAD pmu bindings Bhaskara Budiredla
2021-09-07 18:24 ` Rob Herring [this message]
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