* [PATCH v7 0/2] Add the driver for Intel Keem Bay SoC timer block
@ 2021-09-13 17:49 shruthi.sanil
2021-09-13 17:49 ` [PATCH v7 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer shruthi.sanil
2021-09-13 17:49 ` [PATCH v7 2/2] clocksource: Add Intel Keem Bay timer support shruthi.sanil
0 siblings, 2 replies; 5+ messages in thread
From: shruthi.sanil @ 2021-09-13 17:49 UTC (permalink / raw)
To: daniel.lezcano, tglx, robh+dt, linux-kernel, devicetree
Cc: andriy.shevchenko, kris.pan, mgross, srikanth.thokala,
lakshmi.bai.raja.subramanian, mallikarjunappa.sangannavar,
shruthi.sanil
From: Shruthi Sanil <shruthi.sanil@intel.com>
The timer block supports 1 64-bit free running counter
and 8 32-bit general purpose timers.
Patch 1 holds the device tree binding documentation.
Patch 2 holds the device driver.
This driver is tested on the Keem Bay evaluation module board.
Changes since v6:
- Removed the unused compatible string from the mfd device node
to fix the error thrown by the make dt-binding command.
Changes since v5:
- Created a MFD device for the common configuration register
in the device tree bindings.
- Updated the timer driver with the MFD framework to access the
common configuration register.
Changes since v4:
- Updated the description in the device tree bindings.
- Updated the unit address of all the timers and counter
in the device tree binding.
Changes since v3:
- Update in KConfig file to support COMPILE_TEST for Keem Bay timer.
- Update in device tree bindings to remove status field.
- Update in device tree bindings to remove 64-bit address space for
the child nodes by using non-empty ranges.
Changes since v2:
- Add multi timer support.
- Update in the device tree binding to support multi timers.
- Code optimization.
Changes since v1:
- Add support for KEEMBAY_TIMER to get selected through Kconfig.platforms.
- Add CLOCK_EVT_FEAT_DYNIRQ as part of clockevent feature.
- Avoid overlapping reg regions across 2 device nodes.
- Simplify 2 device nodes as 1 because both are from same IP block.
- Adapt the driver code according to the new simplified devicetree.
Shruthi Sanil (2):
dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer
clocksource: Add Intel Keem Bay timer support
.../bindings/timer/intel,keembay-timer.yaml | 172 ++++++++++++
MAINTAINERS | 5 +
drivers/clocksource/Kconfig | 11 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-keembay.c | 252 ++++++++++++++++++
5 files changed, 441 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
create mode 100644 drivers/clocksource/timer-keembay.c
base-commit: 6880fa6c56601bb8ed59df6c30fd390cc5f6dd8f
--
2.17.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v7 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer
2021-09-13 17:49 [PATCH v7 0/2] Add the driver for Intel Keem Bay SoC timer block shruthi.sanil
@ 2021-09-13 17:49 ` shruthi.sanil
2021-09-16 19:59 ` Rob Herring
2021-09-13 17:49 ` [PATCH v7 2/2] clocksource: Add Intel Keem Bay timer support shruthi.sanil
1 sibling, 1 reply; 5+ messages in thread
From: shruthi.sanil @ 2021-09-13 17:49 UTC (permalink / raw)
To: daniel.lezcano, tglx, robh+dt, linux-kernel, devicetree
Cc: andriy.shevchenko, kris.pan, mgross, srikanth.thokala,
lakshmi.bai.raja.subramanian, mallikarjunappa.sangannavar,
shruthi.sanil
From: Shruthi Sanil <shruthi.sanil@intel.com>
Add Device Tree bindings for the Timer IP, which can be used as
clocksource and clockevent device in the Intel Keem Bay SoC.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Signed-off-by: Shruthi Sanil <shruthi.sanil@intel.com>
---
.../bindings/timer/intel,keembay-timer.yaml | 172 ++++++++++++++++++
1 file changed, 172 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
diff --git a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
new file mode 100644
index 000000000000..80e7785845ac
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
@@ -0,0 +1,172 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Keem Bay SoC Timers
+
+maintainers:
+ - Shruthi Sanil <shruthi.sanil@intel.com>
+
+description: |
+ The Intel Keem Bay timer driver supports 1 free running counter and 8 timers.
+ Each timer is capable of generating inividual interrupt.
+ Both the features are enabled through the timer general config register.
+
+ The parent node represents the common general configuration details and
+ the child nodes represents the counter and timers.
+
+properties:
+ compatible:
+ enum:
+ - simple-mfd
+
+ reg:
+ description: General configuration register address and length.
+ maxItems: 1
+
+ ranges: true
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - ranges
+ - "#address-cells"
+ - "#size-cells"
+
+patternProperties:
+ "^counter@[0-9a-f]+$":
+ type: object
+ description: Properties for Intel Keem Bay counter
+
+ properties:
+ compatible:
+ enum:
+ - intel,keembay-counter
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+ - clocks
+
+ "^timer@[0-9a-f]+$":
+ type: object
+ description: Properties for Intel Keem Bay timer
+
+ properties:
+ compatible:
+ enum:
+ - intel,keembay-timer
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #define KEEM_BAY_A53_TIM
+
+ soc {
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+
+ gpt@20331000 {
+ compatible = "simple-mfd";
+ reg = <0x0 0x20331000 0x0 0xc>;
+ ranges = <0x0 0x0 0x20330000 0xF0>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+
+ counter@e8 {
+ compatible = "intel,keembay-counter";
+ reg = <0xe8 0x8>;
+ clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+ };
+
+ timer@10 {
+ compatible = "intel,keembay-timer";
+ reg = <0x10 0xc>;
+ interrupts = <GIC_SPI 0x3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+ };
+
+ timer@20 {
+ compatible = "intel,keembay-timer";
+ reg = <0x20 0xc>;
+ interrupts = <GIC_SPI 0x4 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+ };
+
+ timer@30 {
+ compatible = "intel,keembay-timer";
+ reg = <0x30 0xc>;
+ interrupts = <GIC_SPI 0x5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+ };
+
+ timer@40 {
+ compatible = "intel,keembay-timer";
+ reg = <0x40 0xc>;
+ interrupts = <GIC_SPI 0x6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+ };
+
+ timer@50 {
+ compatible = "intel,keembay-timer";
+ reg = <0x50 0xc>;
+ interrupts = <GIC_SPI 0x7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+ };
+
+ timer@60 {
+ compatible = "intel,keembay-timer";
+ reg = <0x60 0xc>;
+ interrupts = <GIC_SPI 0x8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+ };
+
+ timer@70 {
+ compatible = "intel,keembay-timer";
+ reg = <0x70 0xc>;
+ interrupts = <GIC_SPI 0x9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+ };
+
+ timer@80 {
+ compatible = "intel,keembay-timer";
+ reg = <0x80 0xc>;
+ interrupts = <GIC_SPI 0xa IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+ };
+ };
+ };
+
+...
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v7 2/2] clocksource: Add Intel Keem Bay timer support
2021-09-13 17:49 [PATCH v7 0/2] Add the driver for Intel Keem Bay SoC timer block shruthi.sanil
2021-09-13 17:49 ` [PATCH v7 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer shruthi.sanil
@ 2021-09-13 17:49 ` shruthi.sanil
1 sibling, 0 replies; 5+ messages in thread
From: shruthi.sanil @ 2021-09-13 17:49 UTC (permalink / raw)
To: daniel.lezcano, tglx, robh+dt, linux-kernel, devicetree
Cc: andriy.shevchenko, kris.pan, mgross, srikanth.thokala,
lakshmi.bai.raja.subramanian, mallikarjunappa.sangannavar,
shruthi.sanil
From: Shruthi Sanil <shruthi.sanil@intel.com>
The Intel Keem Bay timer driver supports clocksource and clockevent
features for the timer IP used in Intel Keem Bay SoC.
The timer block supports 1 free running counter and 8 timers.
The free running counter can be used as a clocksource and
the timers can be used as clockevent. Each timer is capable of
generating individual interrupt.
Both the features are enabled through the timer general config register.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Signed-off-by: Shruthi Sanil <shruthi.sanil@intel.com>
---
MAINTAINERS | 5 +
drivers/clocksource/Kconfig | 11 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-keembay.c | 252 ++++++++++++++++++++++++++++
4 files changed, 269 insertions(+)
create mode 100644 drivers/clocksource/timer-keembay.c
diff --git a/MAINTAINERS b/MAINTAINERS
index eeb4c70b3d5b..1f58350f5f3c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9523,6 +9523,11 @@ F: drivers/crypto/keembay/keembay-ocs-hcu-core.c
F: drivers/crypto/keembay/ocs-hcu.c
F: drivers/crypto/keembay/ocs-hcu.h
+INTEL KEEM BAY TIMER SUPPORT
+M: Shruthi Sanil <shruthi.sanil@intel.com>
+S: Maintained
+F: drivers/clocksource/timer-keembay.c
+
INTEL MANAGEMENT ENGINE (mei)
M: Tomas Winkler <tomas.winkler@intel.com>
L: linux-kernel@vger.kernel.org
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 0f5e3983951a..0dcf2c5aaaf2 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -708,4 +708,15 @@ config MICROCHIP_PIT64B
modes and high resolution. It is used as a clocksource
and a clockevent.
+config KEEMBAY_TIMER
+ bool "Intel Keem Bay timer"
+ depends on ARCH_KEEMBAY || COMPILE_TEST
+ select TIMER_OF
+ help
+ This option enables the support for the Intel Keem Bay
+ general purpose timer and free running counter driver.
+ Each timer can generate an individual interrupt and
+ supports oneshot and periodic modes.
+ The 64-bit counter can be used as a clock source.
+
endmenu
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index c17ee32a7151..ea319063ba47 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -88,3 +88,4 @@ obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o
obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o
obj-$(CONFIG_HYPERV_TIMER) += hyperv_timer.o
obj-$(CONFIG_MICROCHIP_PIT64B) += timer-microchip-pit64b.o
+obj-$(CONFIG_KEEMBAY_TIMER) += timer-keembay.o
diff --git a/drivers/clocksource/timer-keembay.c b/drivers/clocksource/timer-keembay.c
new file mode 100644
index 000000000000..8647a05edf2e
--- /dev/null
+++ b/drivers/clocksource/timer-keembay.c
@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Intel Keem Bay Timer driver
+ *
+ * Copyright (C) 2020 Intel Corporation
+ */
+
+#include <linux/bitops.h>
+#include <linux/idr.h>
+#include <linux/interrupt.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/sizes.h>
+#include <linux/slab.h>
+#include <linux/regmap.h>
+
+#include "timer-of.h"
+
+/* Timer register offset */
+#define TIM_CNT_VAL_OFFSET 0x0
+#define TIM_RELOAD_VAL_OFFSET 0x4
+#define TIM_CONFIG_OFFSET 0x8
+
+/* Bit fields of timer general config register */
+#define TIM_CONFIG_PRESCALER_ENABLE BIT(2)
+#define TIM_CONFIG_COUNTER_ENABLE BIT(0)
+
+/* Bit fields of timer config register */
+#define TIM_CONFIG_INTERRUPT_PENDING BIT(4)
+#define TIM_CONFIG_INTERRUPT_ENABLE BIT(2)
+#define TIM_CONFIG_RESTART BIT(1)
+#define TIM_CONFIG_ENABLE BIT(0)
+
+#define TIM_GEN_MASK GENMASK(31, 12)
+#define TIM_RATING 200
+#define TIM_CLKSRC_MASK_BITS 64
+
+#define TIMER_NAME_SIZE 25
+
+/* Provides a unique ID for each timer */
+static DEFINE_IDA(keembay_timer_ida);
+
+static inline void keembay_timer_enable(void __iomem *base, u32 flags)
+{
+ writel(TIM_CONFIG_ENABLE | flags, base + TIM_CONFIG_OFFSET);
+}
+
+static inline void keembay_timer_disable(void __iomem *base)
+{
+ writel(0x0, base + TIM_CONFIG_OFFSET);
+}
+
+static inline void keembay_timer_update_counter(void __iomem *base, u32 val)
+{
+ writel(val, base + TIM_CNT_VAL_OFFSET);
+ writel(val, base + TIM_RELOAD_VAL_OFFSET);
+}
+
+static inline void keembay_timer_clear_pending_int(void __iomem *base)
+{
+ u32 val;
+
+ val = readl(base + TIM_CONFIG_OFFSET);
+ val &= ~TIM_CONFIG_INTERRUPT_PENDING;
+ writel(val, base + TIM_CONFIG_OFFSET);
+}
+
+static int keembay_timer_set_next_event(unsigned long evt, struct clock_event_device *ce)
+{
+ u32 flags = TIM_CONFIG_INTERRUPT_ENABLE;
+ struct timer_of *to = to_timer_of(ce);
+ void __iomem *tim_base = timer_of_base(to);
+
+ keembay_timer_disable(tim_base);
+ keembay_timer_update_counter(tim_base, evt);
+ keembay_timer_enable(tim_base, flags);
+
+ return 0;
+}
+
+static int keembay_timer_periodic(struct clock_event_device *ce)
+{
+ u32 flags = TIM_CONFIG_INTERRUPT_ENABLE | TIM_CONFIG_RESTART;
+ struct timer_of *to = to_timer_of(ce);
+ void __iomem *tim_base = timer_of_base(to);
+
+ keembay_timer_disable(tim_base);
+ keembay_timer_update_counter(tim_base, timer_of_period(to));
+ keembay_timer_enable(tim_base, flags);
+
+ return 0;
+}
+
+static int keembay_timer_shutdown(struct clock_event_device *ce)
+{
+ struct timer_of *to = to_timer_of(ce);
+
+ keembay_timer_disable(timer_of_base(to));
+
+ return 0;
+}
+
+static irqreturn_t keembay_timer_isr(int irq, void *dev_id)
+{
+ struct clock_event_device *evt = dev_id;
+ struct timer_of *to = to_timer_of(evt);
+ void __iomem *tim_base = timer_of_base(to);
+ u32 val;
+
+ val = readl(tim_base + TIM_CONFIG_OFFSET);
+
+ if (val & TIM_CONFIG_RESTART) {
+ /* Clear interrupt for periodic timer*/
+ keembay_timer_clear_pending_int(tim_base);
+ } else {
+ /* Disable the timer for one shot timer */
+ keembay_timer_disable(tim_base);
+ }
+
+ evt->event_handler(evt);
+
+ return IRQ_HANDLED;
+}
+
+static int __init keembay_clockevent_init(struct device_node *np)
+{
+ struct timer_of *keembay_ce_to;
+ struct regmap *regmap;
+ char *timer_name;
+ int timer_id;
+ int ret;
+ u32 val;
+
+ regmap = device_node_to_regmap(np->parent);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ ret = regmap_read(regmap, TIM_CONFIG_OFFSET, &val);
+ if (ret)
+ return ret;
+
+ /* Prescaler bit must be enabled for the timer to function */
+ if (!(val & TIM_CONFIG_PRESCALER_ENABLE)) {
+ pr_err("%pOF: Prescaler is not enabled\n", np);
+ ret = -ENODEV;
+ }
+
+ keembay_ce_to = kzalloc(sizeof(*keembay_ce_to), GFP_KERNEL);
+ if (!keembay_ce_to)
+ ret = -ENOMEM;
+
+ timer_id = ida_alloc(&keembay_timer_ida, GFP_KERNEL);
+ if (timer_id < 0) {
+ ret = timer_id;
+ goto err_keembay_ce_to_free;
+ }
+
+ timer_name = kasprintf(GFP_KERNEL, "keembay_timer%d", timer_id);
+ if (!timer_name) {
+ ret = -ENOMEM;
+ goto err_free_ida;
+ }
+
+ keembay_ce_to->flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK;
+ keembay_ce_to->clkevt.name = timer_name;
+ keembay_ce_to->clkevt.cpumask = cpumask_of(0);
+ keembay_ce_to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
+ CLOCK_EVT_FEAT_ONESHOT |
+ CLOCK_EVT_FEAT_DYNIRQ;
+ keembay_ce_to->clkevt.rating = TIM_RATING;
+ keembay_ce_to->clkevt.set_next_event = keembay_timer_set_next_event;
+ keembay_ce_to->clkevt.set_state_periodic = keembay_timer_periodic;
+ keembay_ce_to->clkevt.set_state_shutdown = keembay_timer_shutdown;
+ keembay_ce_to->of_irq.handler = keembay_timer_isr;
+ keembay_ce_to->of_irq.flags = IRQF_TIMER;
+
+ ret = timer_of_init(np, keembay_ce_to);
+ if (ret)
+ goto err_timer_name_free;
+
+ ret = regmap_read(regmap, TIM_RELOAD_VAL_OFFSET, &val);
+ if (ret)
+ goto err_timer_name_free;
+
+ keembay_ce_to->of_clk.rate = keembay_ce_to->of_clk.rate / (val + 1);
+
+ clockevents_config_and_register(&keembay_ce_to->clkevt,
+ timer_of_rate(keembay_ce_to),
+ 1,
+ U32_MAX);
+
+ return 0;
+
+err_timer_name_free:
+ kfree(timer_name);
+err_free_ida:
+ ida_free(&keembay_timer_ida, timer_id);
+err_keembay_ce_to_free:
+ kfree(keembay_ce_to);
+
+ return ret;
+}
+
+static struct timer_of keembay_cs_to = {
+ .flags = TIMER_OF_BASE | TIMER_OF_CLOCK,
+};
+
+static u64 notrace keembay_clocksource_read(struct clocksource *cs)
+{
+ return lo_hi_readq(timer_of_base(&keembay_cs_to));
+}
+
+static struct clocksource keembay_counter = {
+ .name = "keembay_sys_counter",
+ .rating = TIM_RATING,
+ .read = keembay_clocksource_read,
+ .mask = CLOCKSOURCE_MASK(TIM_CLKSRC_MASK_BITS),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS |
+ CLOCK_SOURCE_SUSPEND_NONSTOP,
+};
+
+static int __init keembay_clocksource_init(struct device_node *np)
+{
+ struct regmap *regmap;
+ u32 val;
+ int ret;
+
+ regmap = device_node_to_regmap(np->parent);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ ret = regmap_read(regmap, TIM_CONFIG_OFFSET, &val);
+ if (ret)
+ return ret;
+
+ /* Free Running Counter bit must be enabled for counter to function */
+ if (!(val & TIM_CONFIG_COUNTER_ENABLE)) {
+ pr_err("%pOF: free running counter is not enabled\n", np);
+ return -ENODEV;
+ }
+
+ ret = timer_of_init(np, &keembay_cs_to);
+ if (ret)
+ return ret;
+
+ return clocksource_register_hz(&keembay_counter, timer_of_rate(&keembay_cs_to));
+}
+
+TIMER_OF_DECLARE(keembay_clockevent, "intel,keembay-timer", keembay_clockevent_init);
+TIMER_OF_DECLARE(keembay_clocksource, "intel,keembay-counter", keembay_clocksource_init);
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v7 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer
2021-09-13 17:49 ` [PATCH v7 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer shruthi.sanil
@ 2021-09-16 19:59 ` Rob Herring
2021-09-17 4:44 ` Sanil, Shruthi
0 siblings, 1 reply; 5+ messages in thread
From: Rob Herring @ 2021-09-16 19:59 UTC (permalink / raw)
To: shruthi.sanil
Cc: daniel.lezcano, tglx, linux-kernel, devicetree,
andriy.shevchenko, kris.pan, mgross, srikanth.thokala,
lakshmi.bai.raja.subramanian, mallikarjunappa.sangannavar
On Mon, Sep 13, 2021 at 11:19:54PM +0530, shruthi.sanil@intel.com wrote:
> From: Shruthi Sanil <shruthi.sanil@intel.com>
>
> Add Device Tree bindings for the Timer IP, which can be used as
> clocksource and clockevent device in the Intel Keem Bay SoC.
>
> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
> Signed-off-by: Shruthi Sanil <shruthi.sanil@intel.com>
> ---
> .../bindings/timer/intel,keembay-timer.yaml | 172 ++++++++++++++++++
> 1 file changed, 172 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
>
> diff --git a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
> new file mode 100644
> index 000000000000..80e7785845ac
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
> @@ -0,0 +1,172 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Intel Keem Bay SoC Timers
> +
> +maintainers:
> + - Shruthi Sanil <shruthi.sanil@intel.com>
> +
> +description: |
> + The Intel Keem Bay timer driver supports 1 free running counter and 8 timers.
> + Each timer is capable of generating inividual interrupt.
> + Both the features are enabled through the timer general config register.
> +
> + The parent node represents the common general configuration details and
> + the child nodes represents the counter and timers.
> +
> +properties:
> + compatible:
> + enum:
> + - simple-mfd
Removing is not the right solution. What you need is:
items:
- const: intel,keembay-gpt-creg
- const: simple-mfd
> +
> + reg:
> + description: General configuration register address and length.
> + maxItems: 1
> +
> + ranges: true
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - ranges
> + - "#address-cells"
> + - "#size-cells"
> +
> +patternProperties:
> + "^counter@[0-9a-f]+$":
> + type: object
> + description: Properties for Intel Keem Bay counter
> +
> + properties:
> + compatible:
> + enum:
> + - intel,keembay-counter
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + required:
> + - compatible
> + - reg
> + - clocks
> +
> + "^timer@[0-9a-f]+$":
> + type: object
> + description: Properties for Intel Keem Bay timer
> +
> + properties:
> + compatible:
> + enum:
> + - intel,keembay-timer
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #define KEEM_BAY_A53_TIM
> +
> + soc {
> + #address-cells = <0x2>;
> + #size-cells = <0x2>;
> +
> + gpt@20331000 {
> + compatible = "simple-mfd";
> + reg = <0x0 0x20331000 0x0 0xc>;
> + ranges = <0x0 0x0 0x20330000 0xF0>;
> + #address-cells = <0x1>;
> + #size-cells = <0x1>;
> +
> + counter@e8 {
> + compatible = "intel,keembay-counter";
> + reg = <0xe8 0x8>;
> + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> + };
> +
> + timer@10 {
> + compatible = "intel,keembay-timer";
> + reg = <0x10 0xc>;
> + interrupts = <GIC_SPI 0x3 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> + };
> +
> + timer@20 {
> + compatible = "intel,keembay-timer";
> + reg = <0x20 0xc>;
> + interrupts = <GIC_SPI 0x4 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> + };
> +
> + timer@30 {
> + compatible = "intel,keembay-timer";
> + reg = <0x30 0xc>;
> + interrupts = <GIC_SPI 0x5 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> + };
> +
> + timer@40 {
> + compatible = "intel,keembay-timer";
> + reg = <0x40 0xc>;
> + interrupts = <GIC_SPI 0x6 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> + };
> +
> + timer@50 {
> + compatible = "intel,keembay-timer";
> + reg = <0x50 0xc>;
> + interrupts = <GIC_SPI 0x7 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> + };
> +
> + timer@60 {
> + compatible = "intel,keembay-timer";
> + reg = <0x60 0xc>;
> + interrupts = <GIC_SPI 0x8 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> + };
> +
> + timer@70 {
> + compatible = "intel,keembay-timer";
> + reg = <0x70 0xc>;
> + interrupts = <GIC_SPI 0x9 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> + };
> +
> + timer@80 {
> + compatible = "intel,keembay-timer";
> + reg = <0x80 0xc>;
> + interrupts = <GIC_SPI 0xa IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> + };
> + };
> + };
> +
> +...
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH v7 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer
2021-09-16 19:59 ` Rob Herring
@ 2021-09-17 4:44 ` Sanil, Shruthi
0 siblings, 0 replies; 5+ messages in thread
From: Sanil, Shruthi @ 2021-09-17 4:44 UTC (permalink / raw)
To: Rob Herring
Cc: daniel.lezcano, tglx, linux-kernel, devicetree,
andriy.shevchenko, kris.pan, mgross, Thokala, Srikanth,
Raja Subramanian, Lakshmi Bai, Sangannavar, Mallikarjunappa
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Friday, September 17, 2021 1:30 AM
> To: Sanil, Shruthi <shruthi.sanil@intel.com>
> Cc: daniel.lezcano@linaro.org; tglx@linutronix.de; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org;
> andriy.shevchenko@linux.intel.com; kris.pan@linux.intel.com;
> mgross@linux.intel.com; Thokala, Srikanth <srikanth.thokala@intel.com>;
> Raja Subramanian, Lakshmi Bai <lakshmi.bai.raja.subramanian@intel.com>;
> Sangannavar, Mallikarjunappa <mallikarjunappa.sangannavar@intel.com>
> Subject: Re: [PATCH v7 1/2] dt-bindings: timer: Add bindings for Intel Keem
> Bay SoC Timer
>
> On Mon, Sep 13, 2021 at 11:19:54PM +0530, shruthi.sanil@intel.com wrote:
> > From: Shruthi Sanil <shruthi.sanil@intel.com>
> >
> > Add Device Tree bindings for the Timer IP, which can be used as
> > clocksource and clockevent device in the Intel Keem Bay SoC.
> >
> > Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
> > Signed-off-by: Shruthi Sanil <shruthi.sanil@intel.com>
> > ---
> > .../bindings/timer/intel,keembay-timer.yaml | 172 ++++++++++++++++++
> > 1 file changed, 172 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
> > b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
> > new file mode 100644
> > index 000000000000..80e7785845ac
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/timer/intel,keembay-
> timer.yaml
> > @@ -0,0 +1,172 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Intel Keem Bay SoC Timers
> > +
> > +maintainers:
> > + - Shruthi Sanil <shruthi.sanil@intel.com>
> > +
> > +description: |
> > + The Intel Keem Bay timer driver supports 1 free running counter and 8
> timers.
> > + Each timer is capable of generating inividual interrupt.
> > + Both the features are enabled through the timer general config register.
> > +
> > + The parent node represents the common general configuration details
> > + and the child nodes represents the counter and timers.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - simple-mfd
>
> Removing is not the right solution. What you need is:
>
> items:
> - const: intel,keembay-gpt-creg
> - const: simple-mfd
>
Thank You Rob! I'll update accordingly and submit the patch.
> > +
> > + reg:
> > + description: General configuration register address and length.
> > + maxItems: 1
> > +
> > + ranges: true
> > +
> > + "#address-cells":
> > + const: 1
> > +
> > + "#size-cells":
> > + const: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - ranges
> > + - "#address-cells"
> > + - "#size-cells"
> > +
> > +patternProperties:
> > + "^counter@[0-9a-f]+$":
> > + type: object
> > + description: Properties for Intel Keem Bay counter
> > +
> > + properties:
> > + compatible:
> > + enum:
> > + - intel,keembay-counter
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + required:
> > + - compatible
> > + - reg
> > + - clocks
> > +
> > + "^timer@[0-9a-f]+$":
> > + type: object
> > + description: Properties for Intel Keem Bay timer
> > +
> > + properties:
> > + compatible:
> > + enum:
> > + - intel,keembay-timer
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + #define KEEM_BAY_A53_TIM
> > +
> > + soc {
> > + #address-cells = <0x2>;
> > + #size-cells = <0x2>;
> > +
> > + gpt@20331000 {
> > + compatible = "simple-mfd";
> > + reg = <0x0 0x20331000 0x0 0xc>;
> > + ranges = <0x0 0x0 0x20330000 0xF0>;
> > + #address-cells = <0x1>;
> > + #size-cells = <0x1>;
> > +
> > + counter@e8 {
> > + compatible = "intel,keembay-counter";
> > + reg = <0xe8 0x8>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + };
> > +
> > + timer@10 {
> > + compatible = "intel,keembay-timer";
> > + reg = <0x10 0xc>;
> > + interrupts = <GIC_SPI 0x3 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + };
> > +
> > + timer@20 {
> > + compatible = "intel,keembay-timer";
> > + reg = <0x20 0xc>;
> > + interrupts = <GIC_SPI 0x4 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + };
> > +
> > + timer@30 {
> > + compatible = "intel,keembay-timer";
> > + reg = <0x30 0xc>;
> > + interrupts = <GIC_SPI 0x5 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + };
> > +
> > + timer@40 {
> > + compatible = "intel,keembay-timer";
> > + reg = <0x40 0xc>;
> > + interrupts = <GIC_SPI 0x6 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + };
> > +
> > + timer@50 {
> > + compatible = "intel,keembay-timer";
> > + reg = <0x50 0xc>;
> > + interrupts = <GIC_SPI 0x7 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + };
> > +
> > + timer@60 {
> > + compatible = "intel,keembay-timer";
> > + reg = <0x60 0xc>;
> > + interrupts = <GIC_SPI 0x8 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + };
> > +
> > + timer@70 {
> > + compatible = "intel,keembay-timer";
> > + reg = <0x70 0xc>;
> > + interrupts = <GIC_SPI 0x9 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + };
> > +
> > + timer@80 {
> > + compatible = "intel,keembay-timer";
> > + reg = <0x80 0xc>;
> > + interrupts = <GIC_SPI 0xa IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + };
> > + };
> > + };
> > +
> > +...
> > --
> > 2.17.1
> >
> >
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-09-17 4:44 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-13 17:49 [PATCH v7 0/2] Add the driver for Intel Keem Bay SoC timer block shruthi.sanil
2021-09-13 17:49 ` [PATCH v7 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer shruthi.sanil
2021-09-16 19:59 ` Rob Herring
2021-09-17 4:44 ` Sanil, Shruthi
2021-09-13 17:49 ` [PATCH v7 2/2] clocksource: Add Intel Keem Bay timer support shruthi.sanil
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