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[82.27.106.168]) by smtp.gmail.com with ESMTPSA id z17sm2151265wml.24.2021.09.22.07.49.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Sep 2021 07:49:26 -0700 (PDT) Date: Wed, 22 Sep 2021 15:49:05 +0100 From: Jean-Philippe Brucker To: Liu Yi L Cc: alex.williamson@redhat.com, jgg@nvidia.com, hch@lst.de, jasowang@redhat.com, joro@8bytes.org, kevin.tian@intel.com, parav@mellanox.com, lkml@metux.net, pbonzini@redhat.com, lushenming@huawei.com, eric.auger@redhat.com, corbet@lwn.net, ashok.raj@intel.com, yi.l.liu@linux.intel.com, jun.j.tian@intel.com, hao.wu@intel.com, dave.jiang@intel.com, jacob.jun.pan@linux.intel.com, kwankhede@nvidia.com, robin.murphy@arm.com, kvm@vger.kernel.org, iommu@lists.linux-foundation.org, dwmw2@infradead.org, linux-kernel@vger.kernel.org, baolu.lu@linux.intel.com, david@gibson.dropbear.id.au, nicolinc@nvidia.com Subject: Re: [RFC 17/20] iommu/iommufd: Report iova range to userspace Message-ID: References: <20210919063848.1476776-1-yi.l.liu@intel.com> <20210919063848.1476776-18-yi.l.liu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210919063848.1476776-18-yi.l.liu@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Sep 19, 2021 at 02:38:45PM +0800, Liu Yi L wrote: > [HACK. will fix in v2] > > IOVA range is critical info for userspace to manage DMA for an I/O address > space. This patch reports the valid iova range info of a given device. > > Due to aforementioned hack, this info comes from the hacked vfio type1 > driver. To follow the same format in vfio, we also introduce a cap chain > format in IOMMU_DEVICE_GET_INFO to carry the iova range info. [...] > diff --git a/include/uapi/linux/iommu.h b/include/uapi/linux/iommu.h > index 49731be71213..f408ad3c8ade 100644 > --- a/include/uapi/linux/iommu.h > +++ b/include/uapi/linux/iommu.h > @@ -68,6 +68,7 @@ > * +---------------+------------+ > * ... > * @addr_width: the address width of supported I/O address spaces. > + * @cap_offset: Offset within info struct of first cap > * > * Availability: after device is bound to iommufd > */ > @@ -77,9 +78,11 @@ struct iommu_device_info { > #define IOMMU_DEVICE_INFO_ENFORCE_SNOOP (1 << 0) /* IOMMU enforced snoop */ > #define IOMMU_DEVICE_INFO_PGSIZES (1 << 1) /* supported page sizes */ > #define IOMMU_DEVICE_INFO_ADDR_WIDTH (1 << 2) /* addr_wdith field valid */ > +#define IOMMU_DEVICE_INFO_CAPS (1 << 3) /* info supports cap chain */ > __u64 dev_cookie; > __u64 pgsize_bitmap; > __u32 addr_width; > + __u32 cap_offset; We can also add vendor-specific page table and PASID table properties as capabilities, otherwise we'll need giant unions in the iommu_device_info struct. That made me wonder whether pgsize and addr_width should also be separate capabilities for consistency, but this way might be good enough. There won't be many more generic capabilities. I have "output address width" and "PASID width", the rest is specific to Arm and SMMU table formats. Thanks, Jean > }; > > #define IOMMU_DEVICE_GET_INFO _IO(IOMMU_TYPE, IOMMU_BASE + 1) > -- > 2.25.1 >