From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A35E2C433F5 for ; Wed, 22 Sep 2021 21:36:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 78855611C6 for ; Wed, 22 Sep 2021 21:36:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238134AbhIVViB (ORCPT ); Wed, 22 Sep 2021 17:38:01 -0400 Received: from mga01.intel.com ([192.55.52.88]:4683 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238033AbhIVVh7 (ORCPT ); Wed, 22 Sep 2021 17:37:59 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10115"; a="246150924" X-IronPort-AV: E=Sophos;i="5.85,315,1624345200"; d="scan'208";a="246150924" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2021 14:36:28 -0700 X-IronPort-AV: E=Sophos;i="5.85,315,1624345200"; d="scan'208";a="557641969" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2021 14:36:28 -0700 Date: Wed, 22 Sep 2021 21:36:22 +0000 From: Fenghua Yu To: Peter Zijlstra Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Andy Lutomirski , Dave Hansen , Tony Luck , Lu Baolu , Joerg Roedel , Josh Poimboeuf , Dave Jiang , Jacob Jun Pan , Ashok Raj , Ravi V Shankar , iommu@lists.linux-foundation.org, x86 , linux-kernel Subject: Re: [PATCH 4/8] x86/traps: Demand-populate PASID MSR via #GP Message-ID: References: <20210920192349.2602141-1-fenghua.yu@intel.com> <20210920192349.2602141-5-fenghua.yu@intel.com> <20210922210722.GV4323@worktop.programming.kicks-ass.net> <20210922211145.GF5106@worktop.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210922211145.GF5106@worktop.programming.kicks-ass.net> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Peter, On Wed, Sep 22, 2021 at 11:11:45PM +0200, Peter Zijlstra wrote: > On Wed, Sep 22, 2021 at 11:07:22PM +0200, Peter Zijlstra wrote: > > On Mon, Sep 20, 2021 at 07:23:45PM +0000, Fenghua Yu wrote: > > > +static bool fixup_pasid_exception(void) > > > +{ > > > + if (!cpu_feature_enabled(X86_FEATURE_ENQCMD)) > > > + return false; > > > + > > > + return __fixup_pasid_exception(); > > > +} > > That is, shouldn't the above at the very least decode the instruction > causing the #GP and check it's this ENQCMD thing? There were comments on a previous version when we used #GP fixup method: https://lore.kernel.org/linux-iommu/f6d34d59-e6eb-ee9f-d247-8fb2f0e37549@intel.com/ There are three reasons for not decoding the instruction: 1. Parsing the instruction sets bad architectural precedent and is ugly. 2. The instruction could be modified (e.g. JVM) while decoding the instruction. It's. 3. Decoding is more complex than this patch and doesn't worth it. Thanks. -Fenghua