From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27063C433F5 for ; Tue, 28 Sep 2021 23:11:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0FA5C613A5 for ; Tue, 28 Sep 2021 23:11:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243254AbhI1XMh (ORCPT ); Tue, 28 Sep 2021 19:12:37 -0400 Received: from mga09.intel.com ([134.134.136.24]:65166 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243196AbhI1XMV (ORCPT ); Tue, 28 Sep 2021 19:12:21 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10121"; a="224862672" X-IronPort-AV: E=Sophos;i="5.85,330,1624345200"; d="scan'208";a="224862672" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2021 16:10:41 -0700 X-IronPort-AV: E=Sophos;i="5.85,330,1624345200"; d="scan'208";a="478985758" Received: from agluck-desk2.sc.intel.com (HELO agluck-desk2.amr.corp.intel.com) ([10.3.52.146]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2021 16:10:41 -0700 Date: Tue, 28 Sep 2021 16:10:39 -0700 From: "Luck, Tony" To: Dave Hansen Cc: Andy Lutomirski , Fenghua Yu , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "Peter Zijlstra (Intel)" , Lu Baolu , Joerg Roedel , Josh Poimboeuf , Dave Jiang , Jacob Jun Pan , Raj Ashok , "Shankar, Ravi V" , iommu@lists.linux-foundation.org, the arch/x86 maintainers , Linux Kernel Mailing List Subject: Re: [PATCH 4/8] x86/traps: Demand-populate PASID MSR via #GP Message-ID: References: <20210920192349.2602141-1-fenghua.yu@intel.com> <20210920192349.2602141-5-fenghua.yu@intel.com> <1aae375d-3cd4-4ab8-9c64-9e387916e6c0@www.fastmail.com> <035290e6-d914-a113-ea6c-e845d71069cf@intel.com> <3f97b77e-a609-997b-3be7-f44ff7312b0d@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Moving beyond pseudo-code and into compiles-but-probably-broken-code. The intent of the functions below is that Fenghua should be able to do: void fpu__pasid_write(u32 pasid) { u64 msr_val = pasid | MSR_IA32_PASID_VALID; struct ia32_pasid_state *addr; addr = begin_update_one_xsave_feature(current, XFEATURE_PASID, true); addr->pasid = msr_val; finish_update_one_xsave_feature(current); } So here's the two new functions that would be added to arch/x86/kernel/fpu/xstate.c ---- void *begin_update_one_xsave_feature(struct task_struct *tsk, enum xfeature xfeature, bool full) { struct xregs_state *xsave = &tsk->thread.fpu.state.xsave; struct xregs_state *xinit = &init_fpstate.xsave; u64 fmask = 1ull << xfeature; void *addr; BUG_ON(!(xsave->header.xcomp_bv & fmask)); fpregs_lock(); addr = __raw_xsave_addr(xsave, xfeature); if (full || tsk != current) { memcpy(addr, __raw_xsave_addr(xinit, xfeature), xstate_sizes[xfeature]); goto out; } /* could optimize some cases where xsaves() isn't fastest option */ if (!(xsave->header.xfeatures & fmask)) xsaves(xsave, fmask); out: xsave->header.xfeatures |= fmask; return addr; } void finish_update_one_xsave_feature(struct task_struct *tsk) { set_ti_thread_flag(task_thread_info(tsk), TIF_NEED_FPU_LOAD); fpregs_unlock(); } ---- -Tony