From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B694C433EF for ; Wed, 29 Sep 2021 18:07:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 33F4461528 for ; Wed, 29 Sep 2021 18:07:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345664AbhI2SJU (ORCPT ); Wed, 29 Sep 2021 14:09:20 -0400 Received: from mga04.intel.com ([192.55.52.120]:38075 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344304AbhI2SJM (ORCPT ); Wed, 29 Sep 2021 14:09:12 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10122"; a="223118728" X-IronPort-AV: E=Sophos;i="5.85,332,1624345200"; d="scan'208";a="223118728" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2021 11:07:30 -0700 X-IronPort-AV: E=Sophos;i="5.85,332,1624345200"; d="scan'208";a="708463491" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2021 11:07:30 -0700 Date: Wed, 29 Sep 2021 18:07:22 +0000 From: Fenghua Yu To: "Luck, Tony" Cc: Thomas Gleixner , Andy Lutomirski , Peter Zijlstra , Ingo Molnar , Borislav Petkov , Dave Hansen , Lu Baolu , Joerg Roedel , Josh Poimboeuf , Dave Jiang , Jacob Jun Pan , Raj Ashok , "Shankar, Ravi V" , iommu@lists.linux-foundation.org, the arch/x86 maintainers , Linux Kernel Mailing List Subject: Re: [PATCH 5/8] x86/mmu: Add mm-based PASID refcounting Message-ID: References: <87o88jfajo.ffs@tglx> <87k0j6dsdn.ffs@tglx> <87r1d78t2e.ffs@tglx> <75e95acc-6730-ddcf-d722-66e575076256@kernel.org> <877dez8fqu.ffs@tglx> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Tony, On Wed, Sep 29, 2021 at 10:41:42AM -0700, Luck, Tony wrote: > On Wed, Sep 29, 2021 at 07:15:53PM +0200, Thomas Gleixner wrote: > > On Wed, Sep 29 2021 at 09:59, Andy Lutomirski wrote: > > > On 9/29/21 05:28, Thomas Gleixner wrote: > > >> Looking at that patch again, none of this muck in fpu__pasid_write() is > > >> required at all. The whole exception fixup is: > > >> > > >> if (!user_mode(regs)) > > >> return false; > > >> > > >> if (!current->mm->pasid) > > >> return false; > > >> > > >> if (current->pasid_activated) > > >> return false; > > > > > > <-- preemption or BH here: kaboom. > > > > Sigh, this had obviously to run in the early portion of #GP, i.e. before > > enabling interrupts. > > Like this? Obviously with some comment about why this is being done. > > diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c > index a58800973aed..a848a59291e7 100644 > --- a/arch/x86/kernel/traps.c > +++ b/arch/x86/kernel/traps.c > @@ -536,6 +536,12 @@ DEFINE_IDTENTRY_ERRORCODE(exc_general_protection) > unsigned long gp_addr; > int ret; > Add +#ifdef CONFIG_IOMMU_SUPPORT because mm->pasid and current-pasid_activated are defined only if CONFIG_IOMMU_SUPPORT is defined. > + if (user_mode(regs) && current->mm->pasid && !current->pasid_activated) { Maybe need to add "&& cpu_feature_enabled(X86_FEATURE_ENQCMD)" because the IA32_PASID MSR is only used when ENQCMD is enabled? > + current->pasid_activated = 1; > + wrmsrl(MSR_IA32_PASID, current->mm->pasid | MSR_IA32_PASID_VALID); > + return; > + } > + +endif > cond_local_irq_enable(regs); > > if (static_cpu_has(X86_FEATURE_UMIP)) { Thanks. -Fenghua