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From: Mark Brown <broonie@kernel.org>
To: Richard Fitzgerald <rf@opensource.cirrus.com>
Cc: alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org,
	patches@opensource.cirrus.com
Subject: Re: [PATCH 07/16] ASoC: cs42l42: Correct power-up sequence to match datasheet
Date: Fri, 15 Oct 2021 16:02:57 +0100	[thread overview]
Message-ID: <YWmYIQGgxFStAA1x@sirena.org.uk> (raw)
In-Reply-To: <20211015133619.4698-8-rf@opensource.cirrus.com>

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On Fri, Oct 15, 2021 at 02:36:10PM +0100, Richard Fitzgerald wrote:
> The power-up sequence mandated in the datasheet is:

> - VP must turn on first
> - VA, VCP, VL, in any order
> - VD_FILT after VL

>  static const char *const cs42l42_supply_names[CS42L42_NUM_SUPPLIES] = {
> -	"VA",
>  	"VP",
> +	"VA",
>  	"VCP",
> -	"VD_FILT",
>  	"VL",
> +	"VD_FILT",
>  };

If you need the regulators to be turned on in sequence you shouldn't
rely on bulk enable doing it for you - the existing regulator code will
initiate all the enables in parallel and then wait for them all to
complete ramping up so if for example VD_FILT were to ramp more quickly
than the earlier regulators the hardware might notice it getting to
whatever voltage the hardware cares about before them.  The only
sequencing you're getting at the minute is when the enables for the
regulators are toggled and you shouldn't even rely on that.

To get the sequencing guaranteed you should pull VP and VD_FILT out of
the bulk enable and do individual enables for them.

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  reply	other threads:[~2021-10-15 15:03 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-15 13:36 [PATCH 00/16] ASoC: cs42l42: Collection of bugfixes Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 01/16] ASoC: cs42l42: Don't reconfigure the PLL while it is running Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 02/16] ASoC: cs42l42: Always configure both ASP TX channels Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 03/16] ASoC: cs42l42: Correct some register default values Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 04/16] ASoC: cs42l42: Don't set defaults for volatile registers Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 05/16] ASoC: cs42l42: Defer probe if request_threaded_irq() returns EPROBE_DEFER Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 06/16] ASoC: cs42l42: Reset GPIO is mandatory Richard Fitzgerald
2021-10-15 14:30   ` Mark Brown
2021-10-15 13:36 ` [PATCH 07/16] ASoC: cs42l42: Correct power-up sequence to match datasheet Richard Fitzgerald
2021-10-15 15:02   ` Mark Brown [this message]
2021-10-15 13:36 ` [PATCH 08/16] ASoC: cs42l42: Reset and power-down on driver remove() Richard Fitzgerald
2021-10-15 15:04   ` Mark Brown
2021-10-15 13:36 ` [PATCH 09/16] ASoC: cs42l42: Prevent NULL pointer deref in interrupt handler Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 10/16] ASoC: cs42l42: Don't claim to support 192k Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 11/16] ASoC: cs42l42: Use PLL for SCLK > 12.288MHz Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 12/16] ASoC: cs42l42: Allow time for HP/ADC to power-up after enable Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 13/16] ASoC: cs42l42: Set correct SRC MCLK Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 14/16] ASoC: cs42l42: Mark OSC_SWITCH_STATUS register volatile Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 15/16] ASoC: cs42l42: Fix WARN in remove() if running without an interrupt Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 16/16] ASoC: cs42l42: Always enable TS_PLUG and TS_UNPLUG interrupts Richard Fitzgerald
2021-10-15 19:42 ` (subset) [PATCH 00/16] ASoC: cs42l42: Collection of bugfixes Mark Brown

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