On Thu, Oct 21, 2021 at 06:00:21PM +0530, Prathamesh Shete wrote: > Add support for the Tegra234 GPIO bank configuration. > > Signed-off-by: Prathamesh Shete > --- > drivers/gpio/gpio-tegra186.c | 74 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 74 insertions(+) > > diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c > index d38980b9923a..edcc91b35e1e 100644 > --- a/drivers/gpio/gpio-tegra186.c > +++ b/drivers/gpio/gpio-tegra186.c > @@ -14,6 +14,7 @@ > > #include > #include > +#include > > /* security registers */ > #define TEGRA186_GPIO_CTL_SCR 0x0c > @@ -877,6 +878,73 @@ static const struct tegra_gpio_soc tegra194_aon_soc = { > .instance = 1, > }; > > +#define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ > + [TEGRA234_MAIN_GPIO_PORT_##_name] = { \ > + .name = #_name, \ > + .bank = _bank, \ > + .port = _port, \ > + .pins = _pins, \ > + } > + > +static const struct tegra_gpio_port tegra234_main_ports[] = { > + TEGRA234_MAIN_GPIO_PORT(A, 0, 0, 8), > + TEGRA234_MAIN_GPIO_PORT(B, 0, 3, 1), > + TEGRA234_MAIN_GPIO_PORT(C, 5, 1, 8), > + TEGRA234_MAIN_GPIO_PORT(D, 5, 2, 4), > + TEGRA234_MAIN_GPIO_PORT(E, 5, 3, 8), > + TEGRA234_MAIN_GPIO_PORT(F, 5, 4, 6), > + TEGRA234_MAIN_GPIO_PORT(G, 4, 0, 8), > + TEGRA234_MAIN_GPIO_PORT(H, 4, 1, 8), > + TEGRA234_MAIN_GPIO_PORT(I, 4, 2, 7), > + TEGRA234_MAIN_GPIO_PORT(J, 5, 0, 6), > + TEGRA234_MAIN_GPIO_PORT(K, 3, 0, 8), > + TEGRA234_MAIN_GPIO_PORT(L, 3, 1, 4), > + TEGRA234_MAIN_GPIO_PORT(M, 2, 0, 8), > + TEGRA234_MAIN_GPIO_PORT(N, 2, 1, 8), > + TEGRA234_MAIN_GPIO_PORT(P, 2, 2, 8), > + TEGRA234_MAIN_GPIO_PORT(Q, 2, 3, 8), > + TEGRA234_MAIN_GPIO_PORT(R, 2, 4, 6), I stumbled across an old patch I had created a couple of months ago that is very similar to this one. However, at the time I had added a couple more ports here, namely S, T, U and V. Is there a reason why you're not including those here? Thierry