From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58F21C433F5 for ; Sat, 6 Nov 2021 10:29:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3B8CB611C4 for ; Sat, 6 Nov 2021 10:29:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232907AbhKFKbw (ORCPT ); Sat, 6 Nov 2021 06:31:52 -0400 Received: from smtp-out2.suse.de ([195.135.220.29]:45178 "EHLO smtp-out2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229957AbhKFKbr (ORCPT ); Sat, 6 Nov 2021 06:31:47 -0400 Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 2CD501FCA3; Sat, 6 Nov 2021 10:29:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1636194545; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=S/HgqTYuQp+cnwwMHpiHFLT7O0dhDvkwRVXD4HVG28Y=; b=m2yGYxUXCh2FN/a7QFawYQ7gW2iX24ssXPmu49koKojkNIJJCUfEbaKCTPVwRZ4rZJfgGf rk182bt7z0d/vb3nQu5VBlW6EhNVp0E+z0Y0QQ9q/GZpoh4x5MpGEXuYe6MCJbkINX34RB 4qwFtS0kZOCypbJZxR3B46/aFNF82rQ= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1636194545; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=S/HgqTYuQp+cnwwMHpiHFLT7O0dhDvkwRVXD4HVG28Y=; b=Era4DoNoIt4LMO14+7gYM+wqGZAsqxCCwBKICRZTrk01h2Lcbpf7f9jRZKmesmqWI+j2Ik SyL2vAHnDRVrK4Bw== Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 151A413AB3; Sat, 6 Nov 2021 10:29:05 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id Bn/XBPFYhmGnHQAAMHmgww (envelope-from ); Sat, 06 Nov 2021 10:29:05 +0000 Date: Sat, 6 Nov 2021 11:28:54 +0100 From: Borislav Petkov To: Huang Rui Cc: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , linux-pm@vger.kernel.org, Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , linux-kernel@vger.kernel.org, x86@kernel.org Subject: Re: [PATCH v3 01/21] x86/cpufreatures: add AMD Collaborative Processor Performance Control feature flag Message-ID: References: <20211029130241.1984459-1-ray.huang@amd.com> <20211029130241.1984459-2-ray.huang@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20211029130241.1984459-2-ray.huang@amd.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Oct 29, 2021 at 09:02:21PM +0800, Huang Rui wrote: > Add Collaborative Processor Performance Control feature flag for AMD > processors. > > This feature flag will be used on the following amd-pstate driver. The > amd-pstate driver has two approaches to implement the frequency control > behavior. That depends on the CPU hardware implementation. One is "Full > MSR Support" and another is "Shared Memory Support". The feature flag > indicates the current processors with "Full MSR Support". > > Signed-off-by: Huang Rui > --- > arch/x86/include/asm/cpufeatures.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index d0ce5cfd3ac1..f23dc1abd485 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -313,6 +313,7 @@ > #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */ > #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ > #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ > +#define X86_FEATURE_AMD_CPPC (13*32+27) /* Collaborative Processor Performance Control */ I know I have acked this already but an Intel patchset made me look at this again: there's no need to have the vendor name in the feature name: X86_FEATURE_CPPC is perfectly fine. -- Regards/Gruss, Boris. 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