From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DE90C433EF for ; Mon, 15 Nov 2021 14:30:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8316961BD4 for ; Mon, 15 Nov 2021 14:30:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236611AbhKOOdB (ORCPT ); Mon, 15 Nov 2021 09:33:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234216AbhKOOc2 (ORCPT ); Mon, 15 Nov 2021 09:32:28 -0500 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 00BADC061746 for ; Mon, 15 Nov 2021 06:29:31 -0800 (PST) Received: by mail-ed1-x52b.google.com with SMTP id m14so73070757edd.0 for ; Mon, 15 Nov 2021 06:29:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=date:from:to:cc:subject:message-id:mail-followup-to:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=0UUMiNTFIKe2uX/Ero+b5gxkPdB4ZNp4W0PHC433LjQ=; b=CtfLfjT+krpI3rNBs3m6jKFvdItW0jh32PIhCCJJJ58lns5DKon+y/AGNm1kkm65QB aI5lTkbhn76f6tLlmhfSkbot5QS1+vQAPTrbp4KOSNF+9R3aqak9NJILsYRcJUrLaCL/ amKEtAih/gk1FTJ4ZcicuYqKRgXJyjetXMIqE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id :mail-followup-to:references:mime-version:content-disposition :content-transfer-encoding:in-reply-to; bh=0UUMiNTFIKe2uX/Ero+b5gxkPdB4ZNp4W0PHC433LjQ=; b=xgqUKqyVPPXVJjZLlzMCqQxasX6bMV2ZEG8K/9Vet80IBPTD8Whrkxh3VQXcq4JDa2 s8nkdPHWeyfukk7RTwfn8QEEM8ojXD2Q4aJMn1auH0l34MBNXiJjex/zH4TEtiB0NOMO 8cDJtztmU1ZnmXbAJkUWiXofgGJVgkPe5aIbLHQ5knMqkatvjOKkK4AKSBABIMZG5wZU UaW5XcounhmLcrSWrFOX6CAL7YyergxYA/kC4rVxPpvv1yKpeozf+GqjGZ0pYEIdPcpB kI31fv27oPAkx2GDSHNGgIsYHQF972f8lAS/7K9u614W2wbMiC1kwYbIIaIU3glE5phe aQCw== X-Gm-Message-State: AOAM531mengE8oZ9WbskI2UUaqBK3+/7I0Wra3xtA5hPYSQEJbn6dZvD T3dKcv6in6kdLX4B78mzvkbBVfrx7N9GDg== X-Google-Smtp-Source: ABdhPJy7ye2Lcy7XtgIltmNJsEFp9VrxRsZFhHZn733SnYbJbPwuBIUAcRDXvTkI1eolOjbzI0y8qA== X-Received: by 2002:a50:8dcb:: with SMTP id s11mr55166334edh.318.1636986570621; Mon, 15 Nov 2021 06:29:30 -0800 (PST) Received: from phenom.ffwll.local ([2a02:168:57f4:0:efd0:b9e5:5ae6:c2fa]) by smtp.gmail.com with ESMTPSA id s4sm6885990ejn.25.2021.11.15.06.29.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Nov 2021 06:29:30 -0800 (PST) Date: Mon, 15 Nov 2021 15:29:28 +0100 From: Daniel Vetter To: Thomas =?iso-8859-1?Q?Hellstr=F6m?= Cc: Linus Torvalds , Dave Airlie , Daniel Vetter , LKML , dri-devel , Ashutosh Dixit , Matthew Auld , Rodrigo Vivi Subject: Re: [git pull] drm fixes + one missed next for 5.16-rc1 Message-ID: Mail-Followup-To: Thomas =?iso-8859-1?Q?Hellstr=F6m?= , Linus Torvalds , Dave Airlie , LKML , dri-devel , Ashutosh Dixit , Matthew Auld , Rodrigo Vivi References: <1ff1389b-bf4c-cd09-8bfd-d4303d100eee@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1ff1389b-bf4c-cd09-8bfd-d4303d100eee@linux.intel.com> X-Operating-System: Linux phenom 5.10.0-8-amd64 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Nov 15, 2021 at 08:18:53AM +0100, Thomas Hellström wrote: > On 11/14/21 22:19, Linus Torvalds wrote: > > On Sun, Nov 14, 2021 at 1:00 PM Dave Airlie wrote: > > > i915 will no longer be x86-64 only in theory, since Intel now produces > > > PCIe graphics cards using the same hw designs. > > Well, at least in my tree, it still has the "depends on X86", along > > with several other x86-only things (like "select INTEL_GTT", which is > > also x86-only) Yeah it's work in progress and 12+ years of x86 pile up high&deep aren't easy to fix. So please assume the depends on X86 is gone already (and select INTEL_GTT is optional, it's only needed for igfx older than about 8 years or so), but we can't do that yet because all the build boots would run out of air screaming so much :-) > > So by the time that non-x86 theory becomes reality, hopefully the i915 > > people will also have figured out how to do the cache flushing > > properly. > > > > And hopefully that "do it properly" ends up being simply that the > > particular configuration that ends up being portable simply doesn't > > need to do it at all and can statically just not build it, > > sidestepping the issue entirely. > > > > Fingers crossed. > > For non-x86 / discrete graphics, plan is only coherent mappings, although > the "Just not build it" part hasn't been properly figured out yet I guess. > But point taken. Yeah for non-x86 it'll be standard dma-api all the way down. For x86 that ship sailed long ago, but also I'm not clear on why we added a new cache flush primitive for that instead of just continuing to use clflush like we've done since forever. For x86 integrated gpu we _know_ which cpu is there, clflush will exist. So any new horrors shouldn't be needed, not sure why a wbinvd_on_all_cpus slipped in. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch