From: Mark Rutland <mark.rutland@arm.com>
To: Randy Dunlap <rdunlap@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Steven Rostedt <rostedt@goodmis.org>,
Nicolas Saenz Julienne <nsaenzju@redhat.com>,
linux-kernel <linux-kernel@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
rcu@vger.kernel.org, Peter Zijlstra <peterz@infradead.org>,
paulmck@kernel.org, mtosatti <mtosatti@redhat.com>,
frederic <frederic@kernel.org>, Jonathan Corbet <corbet@lwn.net>
Subject: Re: [PATCH v2] Documentation: Fill the gaps about entry/noinstr constraints
Date: Mon, 6 Dec 2021 17:36:51 +0000 [thread overview]
Message-ID: <Ya5KM05XaUBjlthn@FVFF77S0Q05N> (raw)
In-Reply-To: <1158239c-4e65-d3d9-41b3-4fedac856622@infradead.org>
On Fri, Dec 03, 2021 at 07:48:08PM -0800, Randy Dunlap wrote:
> On 12/1/21 12:35, Thomas Gleixner wrote:
> > +Aside of that many architectures have to save register state, e.g. debug or
>
> state (e.g. debug) or
>
> > +cause registers before another exception of the same type can happen. A
>
> ^^^^^ cannot parse (with or without the change to the previous line)
I think the difficulty here is with "cause register"? That' a register which
indicates the cause of an exception, e.g.
* MIPS has `cause` (coprocessor 0 register 13)
* arm64 / AArch64 has `ESR_ELx` (Exception Syndrome Register, ELx)
We could probably clarify this as "exception cause registers" or "exception
status registers", if that helps?
Thanks,
Mark.
next prev parent reply other threads:[~2021-12-06 17:36 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-30 11:28 Question WRT early IRQ/NMI entry code Nicolas Saenz Julienne
2021-11-30 12:05 ` Frederic Weisbecker
2021-11-30 12:50 ` Mark Rutland
2021-11-30 13:47 ` Thomas Gleixner
2021-11-30 14:13 ` Steven Rostedt
2021-11-30 22:31 ` [PATCH] Documentation: Fill the gaps about entry/noinstr constraints Thomas Gleixner
2021-12-01 10:56 ` Mark Rutland
2021-12-01 18:14 ` Thomas Gleixner
2021-12-01 18:23 ` Mark Rutland
2021-12-01 20:28 ` Thomas Gleixner
2021-12-01 20:35 ` [PATCH v2] " Thomas Gleixner
2021-12-02 10:03 ` Mark Rutland
2021-12-03 20:08 ` Paul E. McKenney
2021-12-13 10:36 ` Nicolas Saenz Julienne
2021-12-13 16:41 ` Paul E. McKenney
2021-12-04 3:48 ` Randy Dunlap
2021-12-06 17:36 ` Mark Rutland [this message]
2021-12-06 17:53 ` Paul E. McKenney
2021-12-06 21:24 ` Randy Dunlap
2021-12-06 21:36 ` Paul E. McKenney
2021-11-30 15:13 ` Question WRT early IRQ/NMI entry code Nicolas Saenz Julienne
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