From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E162FC433EF for ; Mon, 29 Nov 2021 00:03:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359831AbhK2AFQ (ORCPT ); Sun, 28 Nov 2021 19:05:16 -0500 Received: from mail-ot1-f46.google.com ([209.85.210.46]:36552 "EHLO mail-ot1-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359717AbhK2ADN (ORCPT ); Sun, 28 Nov 2021 19:03:13 -0500 Received: by mail-ot1-f46.google.com with SMTP id w6-20020a9d77c6000000b0055e804fa524so23035494otl.3; Sun, 28 Nov 2021 15:59:57 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=It1lzkkJ24PwFk2cT/A6Qw7GiP3Z+ld/pMrDenOyPmI=; b=EAnXttIyWv0Rdh33zyRy267/nm36ZpCvlBakU1v8Vp0LcW93sEAx9pwqPd6sLg291H Fo8xW/nQME0K+ONSm44H2ckGXMZoAo5dbSViP/u3EszWE2YxHPqVCwXdTmcqn+F2Ob0B npBjc5e6NqV6I6mrparcMKLD9LbpWU4CgUGDpUrdHfkrlEhCy9J9wZXKOrcaE/pF1Xkw Ws4YbhOPHN+t2kiJTBamyoefaljI7xHW+/fqCjfqUHyU7+F9qlcY1B/yimC6EzmszMb4 ew0QzaKUI4qk1wkSrF6UeZPxwrl/tlNmB5tG5eSUXScpEHS/n8Qm3ZlFC0z/70kNQpBP Y2Ow== X-Gm-Message-State: AOAM533v5I7AMyoNenF3O6XohlBsCwIbK5yvgoegYiJDRAZxEGLFCsUc CJqB9UmEqrUMPrTR3qnWRw== X-Google-Smtp-Source: ABdhPJx0DJedEYbq8QkfDEMq6sCGyXJZjQhR0qhaN7A6+1HmwQOqy9oomiiApp8DlznyZIkXP5mDfw== X-Received: by 2002:a05:6830:22d8:: with SMTP id q24mr40500288otc.170.1638143996812; Sun, 28 Nov 2021 15:59:56 -0800 (PST) Received: from robh.at.kernel.org ([2607:fb90:5fe7:4487:d1b1:985f:1f68:141e]) by smtp.gmail.com with ESMTPSA id s17sm2402501otp.20.2021.11.28.15.59.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Nov 2021 15:59:56 -0800 (PST) Received: (nullmailer pid 2845884 invoked by uid 1000); Sun, 28 Nov 2021 23:59:20 -0000 Date: Sun, 28 Nov 2021 17:59:20 -0600 From: Rob Herring To: Biao Huang Cc: davem@davemloft.net, Jakub Kicinski , Matthias Brugger , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, srv_heupstream@mediatek.com, macpaul.lin@mediatek.com, angelogioacchino.delregno@collabora.com, dkirjanov@suse.de Subject: Re: [PATCH v3 4/7] net-next: dt-bindings: dwmac: Convert mediatek-dwmac to DT schema Message-ID: References: <20211112093918.11061-1-biao.huang@mediatek.com> <20211112093918.11061-5-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211112093918.11061-5-biao.huang@mediatek.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Nov 12, 2021 at 05:39:15PM +0800, Biao Huang wrote: > Convert mediatek-dwmac to DT schema, and delete old mediatek-dwmac.txt. > > Signed-off-by: Biao Huang > --- > .../bindings/net/mediatek-dwmac.txt | 91 ---------- > .../bindings/net/mediatek-dwmac.yaml | 157 ++++++++++++++++++ > 2 files changed, 157 insertions(+), 91 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/net/mediatek-dwmac.txt > create mode 100644 Documentation/devicetree/bindings/net/mediatek-dwmac.yaml > > diff --git a/Documentation/devicetree/bindings/net/mediatek-dwmac.txt b/Documentation/devicetree/bindings/net/mediatek-dwmac.txt > deleted file mode 100644 > index afbcaebf062e..000000000000 > --- a/Documentation/devicetree/bindings/net/mediatek-dwmac.txt > +++ /dev/null > @@ -1,91 +0,0 @@ > -MediaTek DWMAC glue layer controller > - > -This file documents platform glue layer for stmmac. > -Please see stmmac.txt for the other unchanged properties. > - > -The device node has following properties. > - > -Required properties: > -- compatible: Should be "mediatek,mt2712-gmac" for MT2712 SoC > -- reg: Address and length of the register set for the device > -- interrupts: Should contain the MAC interrupts > -- interrupt-names: Should contain a list of interrupt names corresponding to > - the interrupts in the interrupts property, if available. > - Should be "macirq" for the main MAC IRQ > -- clocks: Must contain a phandle for each entry in clock-names. > -- clock-names: The name of the clock listed in the clocks property. These are > - "axi", "apb", "mac_main", "ptp_ref", "rmii_internal" for MT2712 SoC. > -- mac-address: See ethernet.txt in the same directory > -- phy-mode: See ethernet.txt in the same directory > -- mediatek,pericfg: A phandle to the syscon node that control ethernet > - interface and timing delay. > - > -Optional properties: > -- mediatek,tx-delay-ps: TX clock delay macro value. Default is 0. > - It should be defined for RGMII/MII interface. > - It should be defined for RMII interface when the reference clock is from MT2712 SoC. > -- mediatek,rx-delay-ps: RX clock delay macro value. Default is 0. > - It should be defined for RGMII/MII interface. > - It should be defined for RMII interface. > -Both delay properties need to be a multiple of 170 for RGMII interface, > -or will round down. Range 0~31*170. > -Both delay properties need to be a multiple of 550 for MII/RMII interface, > -or will round down. Range 0~31*550. > - > -- mediatek,rmii-rxc: boolean property, if present indicates that the RMII > - reference clock, which is from external PHYs, is connected to RXC pin > - on MT2712 SoC. > - Otherwise, is connected to TXC pin. > -- mediatek,rmii-clk-from-mac: boolean property, if present indicates that > - MT2712 SoC provides the RMII reference clock, which outputs to TXC pin only. > -- mediatek,txc-inverse: boolean property, if present indicates that > - 1. tx clock will be inversed in MII/RGMII case, > - 2. tx clock inside MAC will be inversed relative to reference clock > - which is from external PHYs in RMII case, and it rarely happen. > - 3. the reference clock, which outputs to TXC pin will be inversed in RMII case > - when the reference clock is from MT2712 SoC. > -- mediatek,rxc-inverse: boolean property, if present indicates that > - 1. rx clock will be inversed in MII/RGMII case. > - 2. reference clock will be inversed when arrived at MAC in RMII case, when > - the reference clock is from external PHYs. > - 3. the inside clock, which be sent to MAC, will be inversed in RMII case when > - the reference clock is from MT2712 SoC. > -- assigned-clocks: mac_main and ptp_ref clocks > -- assigned-clock-parents: parent clocks of the assigned clocks > - > -Example: > - eth: ethernet@1101c000 { > - compatible = "mediatek,mt2712-gmac"; > - reg = <0 0x1101c000 0 0x1300>; > - interrupts = ; > - interrupt-names = "macirq"; > - phy-mode ="rgmii-rxid"; > - mac-address = [00 55 7b b5 7d f7]; > - clock-names = "axi", > - "apb", > - "mac_main", > - "ptp_ref", > - "rmii_internal"; > - clocks = <&pericfg CLK_PERI_GMAC>, > - <&pericfg CLK_PERI_GMAC_PCLK>, > - <&topckgen CLK_TOP_ETHER_125M_SEL>, > - <&topckgen CLK_TOP_ETHER_50M_SEL>, > - <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; > - assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>, > - <&topckgen CLK_TOP_ETHER_50M_SEL>, > - <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; > - assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>, > - <&topckgen CLK_TOP_APLL1_D3>, > - <&topckgen CLK_TOP_ETHERPLL_50M>; > - power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>; > - mediatek,pericfg = <&pericfg>; > - mediatek,tx-delay-ps = <1530>; > - mediatek,rx-delay-ps = <1530>; > - mediatek,rmii-rxc; > - mediatek,txc-inverse; > - mediatek,rxc-inverse; > - snps,txpbl = <1>; > - snps,rxpbl = <1>; > - snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>; > - snps,reset-active-low; > - }; > diff --git a/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml b/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml > new file mode 100644 > index 000000000000..2eb4781536f7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml > @@ -0,0 +1,157 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek DWMAC glue layer controller > + > +maintainers: > + - Biao Huang > + > +description: > + This file documents platform glue layer for stmmac. > + > +# We need a select here so we don't match all nodes with 'snps,dwmac' > +select: > + properties: > + compatible: > + contains: > + enum: > + - mediatek,mt2712-gmac > + required: > + - compatible > + > +allOf: > + - $ref: "snps,dwmac.yaml#" > + - $ref: "ethernet-controller.yaml#" Doesn't snps,dwmac.yaml already reference ethernet-controller.yaml? > + > +properties: > + compatible: > + oneOf: > + - items: > + - enum: > + - mediatek,mt2712-gmac > + - const: snps,dwmac-4.20a > + > + clocks: > + items: > + - description: AXI clock > + - description: APB clock > + - description: MAC Main clock > + - description: PTP clock > + - description: RMII reference clock provided by MAC > + > + clock-names: > + items: > + - const: axi > + - const: apb > + - const: mac_main > + - const: ptp_ref > + - const: rmii_internal > + > + mediatek,pericfg: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + The phandle to the syscon node that control ethernet > + interface and timing delay. > + > + mediatek,tx-delay-ps: > + description: > + The internal TX clock delay (provided by this driver) in nanoseconds. > + For MT2712 RGMII interface, Allowed value need to be a multiple of 170, > + or will round down. Range 0~31*170. > + For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550, > + or will round down. Range 0~31*550. > + > + mediatek,rx-delay-ps: > + description: > + The internal RX clock delay (provided by this driver) in nanoseconds. > + For MT2712 RGMII interface, Allowed value need to be a multiple of 170, > + or will round down. Range 0~31*170. > + For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550, > + or will round down. Range 0~31*550. > + > + mediatek,rmii-rxc: > + type: boolean > + description: > + If present, indicates that the RMII reference clock, which is from external > + PHYs, is connected to RXC pin. Otherwise, is connected to TXC pin. > + > + mediatek,rmii-clk-from-mac: > + type: boolean > + description: > + If present, indicates that MAC provides the RMII reference clock, which > + outputs to TXC pin only. > + > + mediatek,txc-inverse: > + type: boolean > + description: > + If present, indicates that > + 1. tx clock will be inversed in MII/RGMII case, > + 2. tx clock inside MAC will be inversed relative to reference clock > + which is from external PHYs in RMII case, and it rarely happen. > + 3. the reference clock, which outputs to TXC pin will be inversed in RMII case > + when the reference clock is from MAC. > + > + mediatek,rxc-inverse: > + type: boolean > + description: > + If present, indicates that > + 1. rx clock will be inversed in MII/RGMII case. > + 2. reference clock will be inversed when arrived at MAC in RMII case, when > + the reference clock is from external PHYs. > + 3. the inside clock, which be sent to MAC, will be inversed in RMII case when > + the reference clock is from MAC. > + > +required: > + - compatible > + - reg > + - interrupts > + - interrupt-names > + - clocks > + - clock-names > + - phy-mode > + - mediatek,pericfg > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + #include > + > + eth: ethernet@1101c000 { > + compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a"; > + reg = <0x1101c000 0x1300>; > + interrupts = ; > + interrupt-names = "macirq"; > + phy-mode ="rgmii-rxid"; > + mac-address = [00 55 7b b5 7d f7]; > + clock-names = "axi", > + "apb", > + "mac_main", > + "ptp_ref", > + "rmii_internal"; > + clocks = <&pericfg CLK_PERI_GMAC>, > + <&pericfg CLK_PERI_GMAC_PCLK>, > + <&topckgen CLK_TOP_ETHER_125M_SEL>, > + <&topckgen CLK_TOP_ETHER_50M_SEL>, > + <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; > + assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>, > + <&topckgen CLK_TOP_ETHER_50M_SEL>, > + <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>, > + <&topckgen CLK_TOP_APLL1_D3>, > + <&topckgen CLK_TOP_ETHERPLL_50M>; > + power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>; > + mediatek,pericfg = <&pericfg>; > + mediatek,tx-delay-ps = <1530>; > + snps,txpbl = <1>; > + snps,rxpbl = <1>; > + snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>; > + snps,reset-delays-us = <0 10000 10000>; > + }; > -- > 2.25.1 > >