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[213.175.37.12]) by smtp.gmail.com with ESMTPSA id b6sm7152187wmq.45.2021.12.08.13.35.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Dec 2021 13:35:09 -0800 (PST) Date: Wed, 8 Dec 2021 22:35:07 +0100 From: Jiri Olsa To: German Gomez Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org, John Garry , Will Deacon , Mathieu Poirier , Leo Yan , Mark Rutland , Alexander Shishkin , Namhyung Kim , linux-arm-kernel@lists.infradead.org, linux-csky@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v1 1/4] perf tools: Prevent out-of-bounds access to registers Message-ID: References: <20211201123334.679131-1-german.gomez@arm.com> <20211201123334.679131-2-german.gomez@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211201123334.679131-2-german.gomez@arm.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Dec 01, 2021 at 12:33:29PM +0000, German Gomez wrote: > The size of the cache of register values is arch-dependant > (PERF_REGS_MAX). This has the potential of causing an out-of-bounds > access in the function "perf_reg_value" if the local architecture > contains less registers than the one the perf.data file was recorded on. > > Since the maximum number of registers is bound by the bitmask "u64 > cache_mask", and the size of the cache when running under x86 systems is > 64 already, fix the size to 64 and add a range-check to the function > "perf_reg_value" to prevent out-of-bounds access. > > Signed-off-by: German Gomez Acked-by: Jiri Olsa thanks, jirka > --- > tools/perf/util/event.h | 5 ++++- > tools/perf/util/perf_regs.c | 3 +++ > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/tools/perf/util/event.h b/tools/perf/util/event.h > index 95ffed663..c59331eea 100644 > --- a/tools/perf/util/event.h > +++ b/tools/perf/util/event.h > @@ -44,13 +44,16 @@ struct perf_event_attr; > /* perf sample has 16 bits size limit */ > #define PERF_SAMPLE_MAX_SIZE (1 << 16) > > +/* number of register is bound by the number of bits in regs_dump::mask (64) */ > +#define PERF_SAMPLE_REGS_CACHE_SIZE (8 * sizeof(u64)) > + > struct regs_dump { > u64 abi; > u64 mask; > u64 *regs; > > /* Cached values/mask filled by first register access. */ > - u64 cache_regs[PERF_REGS_MAX]; > + u64 cache_regs[PERF_SAMPLE_REGS_CACHE_SIZE]; > u64 cache_mask; > }; > > diff --git a/tools/perf/util/perf_regs.c b/tools/perf/util/perf_regs.c > index 5ee47ae15..06a7461ba 100644 > --- a/tools/perf/util/perf_regs.c > +++ b/tools/perf/util/perf_regs.c > @@ -25,6 +25,9 @@ int perf_reg_value(u64 *valp, struct regs_dump *regs, int id) > int i, idx = 0; > u64 mask = regs->mask; > > + if ((u64)id >= PERF_SAMPLE_REGS_CACHE_SIZE) > + return -EINVAL; > + > if (regs->cache_mask & (1ULL << id)) > goto out; > > -- > 2.25.1 >