From: Borislav Petkov <bp@alien8.de>
To: Yazen Ghannam <yazen.ghannam@amd.com>
Cc: linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
mchehab@kernel.org, tony.luck@intel.com, james.morse@arm.com,
rric@kernel.org, Smita.KoralahalliChannabasappa@amd.com,
william.roche@oracle.com
Subject: Re: [PATCH 3/4] EDAC/amd64: Check register values from all UMCs
Date: Fri, 10 Dec 2021 13:34:19 +0100 [thread overview]
Message-ID: <YbNJSyv4GdC+SUSD@zn.tnic> (raw)
In-Reply-To: <20211208174356.1997855-4-yazen.ghannam@amd.com>
On Wed, Dec 08, 2021 at 05:43:55PM +0000, Yazen Ghannam wrote:
> Loop over all UMCs and create bitmasks to check the values of the
> DIMM_CFG and UMC_CFG registers rather than just checking the values from
> the first two UMCs.
Do not talk about what your patch does in the commit message - that
should hopefully be visible in the diff itself. Rather, talk about *why*
you're doing what you're doing.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
next prev parent reply other threads:[~2021-12-10 12:34 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-08 17:43 [PATCH 0/4] AMD Family 19h Models 10h-1Fh Updates Yazen Ghannam
2021-12-08 17:43 ` [PATCH 1/4] EDAC: Add RDDR5 and LRDDR5 memory types Yazen Ghannam
2021-12-08 17:43 ` [PATCH 2/4] EDAC/amd64: Add support for AMD Family 19h Models 10h-1Fh and A0h-AFh Yazen Ghannam
2021-12-08 17:43 ` [PATCH 3/4] EDAC/amd64: Check register values from all UMCs Yazen Ghannam
2021-12-10 12:34 ` Borislav Petkov [this message]
2021-12-13 17:24 ` Yazen Ghannam
2021-12-08 17:43 ` [PATCH 4/4] EDAC/amd64: Add DDR5 support and related register changes Yazen Ghannam
2021-12-10 12:41 ` Borislav Petkov
2021-12-13 17:46 ` Yazen Ghannam
2021-12-14 16:22 ` Borislav Petkov
2021-12-10 12:44 ` [PATCH 0/4] AMD Family 19h Models 10h-1Fh Updates Borislav Petkov
2021-12-13 17:23 ` Yazen Ghannam
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