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Wysocki" , the arch/x86 maintainers , Borislav Petkov , Ingo Molnar Cc: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , Peter Zijlstra , Giovanni Gherdovich , Linux PM , "Sharma, Deepak" , "Deucher, Alexander" , "Limonciello, Mario" , Steven Noonan , "Fontenot, Nathan" , "Su, Jinzhou (Joe)" , "Du, Xiaojian" , Linux Kernel Mailing List Subject: Re: [PATCH v5 02/22] x86/msr: add AMD CPPC MSR definitions Message-ID: References: <20211130123641.1449041-1-ray.huang@amd.com> <20211130123641.1449041-3-ray.huang@amd.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: HK0PR01CA0063.apcprd01.prod.exchangelabs.com (2603:1096:203:a6::27) To DM5PR12MB2504.namprd12.prod.outlook.com (2603:10b6:4:b5::19) MIME-Version: 1.0 Received: from amd.com (165.204.134.251) by HK0PR01CA0063.apcprd01.prod.exchangelabs.com (2603:1096:203:a6::27) with Microsoft SMTP Server (version=TLS1_2, cipher=) via Frontend Transport; Fri, 17 Dec 2021 03:10:04 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3a46d0f9-16aa-4867-64eb-08d9c10abc81 X-MS-TrafficTypeDiagnostic: DM6PR12MB3468:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?EHcRj2iqfg+4rdAA1dd0tk9OgxWPOG2Q9R7OqM40ZN4cyd+HPe2YIazhA5yP?= =?us-ascii?Q?slXcRAPseQysTvUvUylRCSPxTwf5xwb4lkYDHeInHSxu0ZDeMGq/Zz3p+j7i?= =?us-ascii?Q?OgmzWMG75M2Ui1YJIiglBqTZKUsEzqf4WsUNog27wvZ6z2DvkHX4Yh+DcQYP?= =?us-ascii?Q?q+FIkefAaollHdgMxeo2DCBbeH5fFtL+lUnv/HSw4uUyY9sSCANVInOee5J1?= =?us-ascii?Q?YVnuv+SD9LKOyiOSDyb1/CtdxKSQ8w6uIckrwg9g8k1r7Txd/4OQyHfdLi9l?= =?us-ascii?Q?fIBFaBEi5E5TbPJnoFLFHUMPUbly7DeGPIi9hIK2gzgdSblw2FWUfoEvyWOk?= =?us-ascii?Q?f6wLs6A5ztGpgPIJK6VdQdTbXvupCOGXJB1rnRS743LC8oBKpN/eSz/04ZBG?= =?us-ascii?Q?wEGW2rob6Eh7SMaztZDG71s3IDm/dr3IxUkNa7eLM3LrSp+DUysev//fB4fO?= =?us-ascii?Q?KBeJYH98essGgjZkRRYAQRlGlkHK44p1o9U8iy3mlun857lOpo026GxG6L+h?= =?us-ascii?Q?VOxXSondhRuZrMyznBmdt1jORNcLrMcLOWaUxD8ok3Nj3G9SAUUgQvA4dIxE?= =?us-ascii?Q?byrPMYxLp5yB0eLsIoxi5+0TizoqK+D3+0ByfkNQIiiH1XnRLaNgLiudutjO?= =?us-ascii?Q?2DAS/ti+NQ76O5S85CSFpd4FVvD3mktEO4h7xTw1/4UjV0ZP8I75pAVN+eCe?= =?us-ascii?Q?TT1242D4OfTrEhGlDmhfafkNZ/OQGFtfJZEk9uMeDsnQWv+ex/QEtPpUJkco?= =?us-ascii?Q?cbQcYddeih0NCcNFFbGWzejmofebk4wOpuko6GKjTLrgYzN9urf7+sqSae5f?= =?us-ascii?Q?1sAwt/c9NsX6jQoSFnKs+mpnq5fejhwENdXJWI4ifeddhyig3HYlIKEj0CuP?= =?us-ascii?Q?NJ4nNrk1sP392uSwkL6bnCAF25T/YzBBvWNA5SePLggxjlaiVXJOfnV9Afqi?= =?us-ascii?Q?q1SYTjmk4ttF4gSPiwJA1Dg1QFfWjUYgfQDB031gYyyV/4IAGGN0EFENnZIv?= =?us-ascii?Q?AYZitd9ppT1t1O+8PaenyPrKB/1Az9HVNHW5mj0jU9RuRlQSrdE29I6riyOX?= =?us-ascii?Q?XfcEy7yJrlxrLTGWNvs4D0bdz2a3Fz/TsVpEv4Whj/gxDuvyd8fV//ivagdY?= =?us-ascii?Q?EL1q0BBEKzR5uT6vtAsk0OuxpHJuT7IRazVEBzQpYfLWzpr0kg0NmGod2ise?= =?us-ascii?Q?HUte5xhg92qc622kppVLWC9U3mFJIIdhtBuxILzVyenqc+B5687sdOK1/wK0?= =?us-ascii?Q?3GyA9fQDMRipUfZcUH4vu8VmCEaYMPGs9npTpbNtNR7L+dNuSDLEy/ev7X2s?= =?us-ascii?Q?DsNwm2A8IblaXpnLdbpvCup0RqHYnMdCw9vApYrLXmUtGjHJ/ELjnH1CdQy2?= =?us-ascii?Q?oacCS/rt+h43jCLF9q3wCYPGRJtCqRT47C5+gamb+pvH/bLAHZd9mOjZ6N7h?= =?us-ascii?Q?yReQ+2k5sO/dhLNZf8s2NpBi9DNbIwO5Vjz3zqlb5b4ZlxFQ/P6si05RtMgj?= =?us-ascii?Q?6bla4Gn77mcgcgOyOH/0rkmSGxC2sIsQ+YCo5RXZavHT5p/Bzszs7UWKsqPH?= =?us-ascii?Q?lyaQtPEonjP69YoKmyFdcz2mQyMc2WdwcSqdIYwVSKMI1gFT0NLX9sH0Um+9?= =?us-ascii?Q?qXhnyXgT5oFWJpJ1e49xMoQ=3D?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3a46d0f9-16aa-4867-64eb-08d9c10abc81 X-MS-Exchange-CrossTenant-AuthSource: DM5PR12MB2504.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Dec 2021 03:10:11.1378 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: OUvyuqgTA0zNS+f7Y/AMI3SyM9qlNbHPaKg9iOZmanxRmzC7LaPbsbdx1C4N2e982fENHHuiUc6s4zr6rq9Rhg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3468 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Dec 17, 2021 at 01:23:22AM +0800, Rafael J. Wysocki wrote: > On Tue, Nov 30, 2021 at 1:37 PM Huang Rui wrote: > > > > AMD CPPC (Collaborative Processor Performance Control) function uses MSR > > registers to manage the performance hints. So add the MSR register macro > > here. > > > > Signed-off-by: Huang Rui > > I guess I can take this one if there are no objections from the x86 > maintainers, but it would be nice to receive an ACK from one of them. > Hi x86 maintainers, the MSR register descriptions are documented at Processor Programming Reference (PPR) for AMD Family 19h Model 51h, Revision A1 Processors: https://www.amd.com/system/files/TechDocs/56569-A1-PUB.zip Thanks, Ray > > --- > > arch/x86/include/asm/msr-index.h | 17 +++++++++++++++++ > > 1 file changed, 17 insertions(+) > > > > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > > index 01e2650b9585..e7945ef6a8df 100644 > > --- a/arch/x86/include/asm/msr-index.h > > +++ b/arch/x86/include/asm/msr-index.h > > @@ -486,6 +486,23 @@ > > > > #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f > > > > +/* AMD Collaborative Processor Performance Control MSRs */ > > +#define MSR_AMD_CPPC_CAP1 0xc00102b0 > > +#define MSR_AMD_CPPC_ENABLE 0xc00102b1 > > +#define MSR_AMD_CPPC_CAP2 0xc00102b2 > > +#define MSR_AMD_CPPC_REQ 0xc00102b3 > > +#define MSR_AMD_CPPC_STATUS 0xc00102b4 > > + > > +#define CAP1_LOWEST_PERF(x) (((x) >> 0) & 0xff) > > +#define CAP1_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) > > +#define CAP1_NOMINAL_PERF(x) (((x) >> 16) & 0xff) > > +#define CAP1_HIGHEST_PERF(x) (((x) >> 24) & 0xff) > > + > > +#define REQ_MAX_PERF(x) (((x) & 0xff) << 0) > > +#define REQ_MIN_PERF(x) (((x) & 0xff) << 8) > > +#define REQ_DES_PERF(x) (((x) & 0xff) << 16) > > +#define REQ_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) > > + > > /* Fam 17h MSRs */ > > #define MSR_F17H_IRPERF 0xc00000e9 > > > > -- > > 2.25.1 > >