From: Jisheng Zhang <jszhang@kernel.org>
To: "Jingoo Han" <jingoohan1@gmail.com>,
"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] PCI: dwc: Fix integrated MSI Receiver mask reg setting during resume
Date: Sun, 23 Jan 2022 20:02:42 +0800 [thread overview]
Message-ID: <Ye1D4lYAIpDe7qAN@xhacker> (raw)
In-Reply-To: <20211226074019.2556-1-jszhang@kernel.org>
On Sun, Dec 26, 2021 at 03:40:19PM +0800, Jisheng Zhang wrote:
> If the host which makes use of the IP's integrated MSI Receiver losts
> power during suspend, we call dw_pcie_setup_rc() to reinit the RC. But
> dw_pcie_setup_rc() always set the pp->irq_mask[ctrl] as ~0, so the mask
> register is always set as 0xffffffff incorrectly, thus the MSI can't
> work after resume.
>
> Fix this issue by moving pp->irq_mask[ctrl] initialization to
> dw_pcie_host_init(), so we can correctly set the mask reg during both
> boot and resume.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Hi all,
This patch can still be applied to the latest linus tree. Do you want
me to rebase and send out a new version?
Without this patch, dwc host MSI interrupt(if use the IP's integrated
MSI receiver) can't work after resume. Could it be picked up as a fix
for v5.17?
Thanks
> ---
> drivers/pci/controller/dwc/pcie-designware-host.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index f4755f3a03be..2fa86f32d964 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -362,6 +362,12 @@ int dw_pcie_host_init(struct pcie_port *pp)
> if (ret < 0)
> return ret;
> } else if (pp->has_msi_ctrl) {
> + u32 ctrl, num_ctrls;
> +
> + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
> + for (ctrl = 0; ctrl < num_ctrls; ctrl++)
> + pp->irq_mask[ctrl] = ~0;
> +
> if (!pp->msi_irq) {
> pp->msi_irq = platform_get_irq_byname_optional(pdev, "msi");
> if (pp->msi_irq < 0) {
> @@ -541,7 +547,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>
> /* Initialize IRQ Status array */
> for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
> - pp->irq_mask[ctrl] = ~0;
> dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
> (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
> pp->irq_mask[ctrl]);
> --
> 2.34.1
>
next prev parent reply other threads:[~2022-01-23 12:10 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-26 7:40 [PATCH] PCI: dwc: Fix integrated MSI Receiver mask reg setting during resume Jisheng Zhang
2022-01-10 3:21 ` Hongxing Zhu
2022-01-23 12:02 ` Jisheng Zhang [this message]
2022-02-23 11:46 ` Lorenzo Pieralisi
2022-02-23 16:06 ` Jisheng Zhang
2022-02-24 14:08 ` Lorenzo Pieralisi
2022-02-26 9:15 ` Jisheng Zhang
2022-03-02 10:37 ` Lorenzo Pieralisi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Ye1D4lYAIpDe7qAN@xhacker \
--to=jszhang@kernel.org \
--cc=bhelgaas@google.com \
--cc=gustavo.pimentel@synopsys.com \
--cc=jingoohan1@gmail.com \
--cc=kw@linux.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).