On Thu, Feb 03, 2022 at 09:42:10PM +0530, Manivannan Sadhasivam wrote: > On Thu, Feb 03, 2022 at 03:21:50PM +0100, Jonathan Neuschäfer wrote: > > In order that the end of a clk_div_table can be detected, it must be > > terminated with a sentinel element (.div = 0). > > > > Fixes: d47317ca4ade1 ("clk: actions: Add S700 SoC clock support") > > Fixes: d85d20053e195 ("clk: actions: Add S900 SoC clock support") > > Signed-off-by: Jonathan Neuschäfer > > --- > > > > I'm not so sure about usb3_mac_div_table. Maybe the { 0, 8 } element was > > meant to be { 0, 0 }? I'd appreciate if someone with access to the > > datasheet or hardware could verify what's correct. > > USB3 factor table is not documented in the datasheet I have access to. But by > looking at the value, it looks to be a typo. So please change the last entry. Okay. > With that, > > Reviewed-by: Manivannan Sadhasivam Thanks! Jonathan