From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A2F4C43217 for ; Tue, 15 Feb 2022 17:15:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242376AbiBORP1 (ORCPT ); Tue, 15 Feb 2022 12:15:27 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:41016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242362AbiBORPY (ORCPT ); Tue, 15 Feb 2022 12:15:24 -0500 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D63311ADEA; Tue, 15 Feb 2022 09:15:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644945312; x=1676481312; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=0RT88KVIkpcIt49KegmwACI0CL9gcweN2MoVMiIbVRY=; b=Ao0Y02dPb3pRuLZzfaEZnYMMkBBsWLxSaPYsbMLL0D9MpkzLQ39YaH+1 ZvXwnOefsgEeyS1M3HvdXVtf4F0I3vT4UGyVeek641LLxmM4IgGsBo2BC 3hubo6iaqCXuvDQzNiGkSFkxmLnLqcVaJPDzYOyGkwSkjEv77MLq0/1Nw yURhrTO8z7y8SW0qtwpqkFkmDb5RFqJIFhfmCYzA28YXQDvbRJNS2LCa2 mwKIk1PPxuykw/80CqsEg6r9ELwU6jRMgegiWmxdXSBWduFgFOHLUHDHm 7tXHKockhkdhHTa/5UBJnuCb7141dH97E2dZxphT9wKef4MIaNlcXZqb2 w==; X-IronPort-AV: E=McAfee;i="6200,9189,10259"; a="274975411" X-IronPort-AV: E=Sophos;i="5.88,371,1635231600"; d="scan'208";a="274975411" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 09:12:41 -0800 X-IronPort-AV: E=Sophos;i="5.88,371,1635231600"; d="scan'208";a="486258571" Received: from smile.fi.intel.com ([10.237.72.59]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 09:12:34 -0800 Received: from andy by smile.fi.intel.com with local (Exim 4.95) (envelope-from ) id 1nK1MY-0050PZ-TS; Tue, 15 Feb 2022 19:11:38 +0200 Date: Tue, 15 Feb 2022 19:11:38 +0200 From: Andy Shevchenko To: Lee Jones Cc: Wolfram Sang , Jean Delvare , Heiner Kallweit , Hans de Goede , Linus Walleij , Tan Jui Nee , Kate Hsuan , Jonathan Yong , linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, linux-i2c@vger.kernel.org, linux-gpio@vger.kernel.org, platform-driver-x86@vger.kernel.org, Borislav Petkov , Mauro Carvalho Chehab , Tony Luck , James Morse , Robert Richter , Jean Delvare , Peter Tyser , Mika Westerberg , Andy Shevchenko , Mark Gross , Henning Schild Subject: Re: [PATCH v4 5/8] mfd: lpc_ich: Add support for pinctrl in non-ACPI system Message-ID: References: <20220131151346.45792-1-andriy.shevchenko@linux.intel.com> <20220131151346.45792-6-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Feb 15, 2022 at 04:54:00PM +0000, Lee Jones wrote: > On Mon, 31 Jan 2022, Andy Shevchenko wrote: Thank you for the review, my answers below. ... > > +static struct resource apl_gpio_resources[APL_GPIO_NR_DEVICES][2] = { > > + [APL_GPIO_NORTH] = { > > + DEFINE_RES_MEM(APL_GPIO_NORTH_OFFSET, 0x1000), > > Are these 0x1000's being over-written in lpc_ich_init_pinctrl()? > > If so, why pre-initialise? You mean to pre-initialize the offsets, but leave the length to be added in the function? It can be done, but it feels inconsistent, since we would have offsets and lengths in different places for the same thingy. That said, I prefer current way for the sake of consistency. > > + DEFINE_RES_IRQ(APL_GPIO_IRQ), > > + }, ... > > +/* The order must be in sync with apl_pinctrl_soc_data */ > > Why does the order matter if you've pre-enumerated them all? Indeed. I will drop the confusing comment in the next version. -- With Best Regards, Andy Shevchenko