From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Rob Herring <robh@kernel.org>
Cc: shruthi.sanil@intel.com, daniel.lezcano@linaro.org,
tglx@linutronix.de, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, mgross@linux.intel.com,
srikanth.thokala@intel.com,
lakshmi.bai.raja.subramanian@intel.com,
mallikarjunappa.sangannavar@intel.com
Subject: Re: [PATCH v8 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer
Date: Wed, 23 Feb 2022 13:30:38 +0200 [thread overview]
Message-ID: <YhYa3tlTEcLct2xu@smile.fi.intel.com> (raw)
In-Reply-To: <YhVuJaf3AJ1c6TpT@robh.at.kernel.org>
On Tue, Feb 22, 2022 at 05:13:41PM -0600, Rob Herring wrote:
> On Tue, Feb 22, 2022 at 03:26:53PM +0530, shruthi.sanil@intel.com wrote:
> > From: Shruthi Sanil <shruthi.sanil@intel.com>
> >
> > Add Device Tree bindings for the Timer IP, which can be used as
> > clocksource and clockevent device in the Intel Keem Bay SoC.
...
> > + soc {
> > + #address-cells = <0x2>;
> > + #size-cells = <0x2>;
> > +
> > + gpt@20331000 {
> > + compatible = "intel,keembay-gpt-creg", "simple-mfd";
>
> It looks like you are splitting things based on Linux implementation
> details. Does this h/w block have different combinations of timers and
> counters? If not, then you don't need the child nodes at all. There's
> plenty of h/w blocks that get used as both a clocksource and clockevent.
>
> Maybe I already raised this, but assume I don't remember and this patch
> needs to address any questions I already asked.
I dunno if I mentioned that hardware seems to have 5 or so devices behind
the block, so ideally it should be one device node that represents the global
register spaces and several children nodes.
However, I am not familiar with the established practices in DT world, but
above seems to me the right thing to do since it describes the hardware as
is (without any linuxisms).
> > + reg = <0x0 0x20331000 0x0 0xc>;
> > + ranges = <0x0 0x0 0x20330000 0xF0>;
> > + #address-cells = <0x1>;
> > + #size-cells = <0x1>;
> > +
> > + counter@e8 {
> > + compatible = "intel,keembay-counter";
> > + reg = <0xe8 0x8>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + };
> > +
> > + timer@30 {
> > + compatible = "intel,keembay-timer";
> > + reg = <0x30 0xc>;
> > + interrupts = <GIC_SPI 0x5 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + };
> > + };
> > + };
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2022-02-23 11:31 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-22 9:56 [PATCH v8 0/2] Add the driver for Intel Keem Bay SoC timer block shruthi.sanil
2022-02-22 9:56 ` [PATCH v8 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer shruthi.sanil
2022-02-22 23:13 ` Rob Herring
2022-02-23 7:49 ` Sanil, Shruthi
2022-02-23 11:30 ` Andy Shevchenko [this message]
2022-03-07 22:33 ` Rob Herring
2022-03-08 10:13 ` Andy Shevchenko
2022-03-18 5:36 ` Sanil, Shruthi
2022-06-06 17:47 ` Sanil, Shruthi
2022-06-16 3:42 ` Sanil, Shruthi
2022-02-22 9:56 ` [PATCH v8 2/2] clocksource: Add Intel Keem Bay timer support shruthi.sanil
2022-02-28 7:39 ` Sanil, Shruthi
2022-03-01 21:09 ` Daniel Lezcano
2022-03-02 10:12 ` Sanil, Shruthi
2022-03-02 10:24 ` Daniel Lezcano
2022-03-02 16:07 ` Sanil, Shruthi
2022-03-02 16:26 ` Daniel Lezcano
2022-03-03 6:18 ` Sanil, Shruthi
2022-03-03 10:17 ` Daniel Lezcano
2022-03-03 10:23 ` Sanil, Shruthi
2022-03-03 10:48 ` andriy.shevchenko
2022-03-03 10:51 ` Sanil, Shruthi
2022-03-03 10:47 ` andriy.shevchenko
2022-03-03 13:04 ` Daniel Lezcano
2022-03-02 13:54 ` andriy.shevchenko
2022-03-02 13:53 ` Andy Shevchenko
2022-03-02 15:58 ` Daniel Lezcano
2022-03-02 16:07 ` Andy Shevchenko
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=YhYa3tlTEcLct2xu@smile.fi.intel.com \
--to=andriy.shevchenko@linux.intel.com \
--cc=daniel.lezcano@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=lakshmi.bai.raja.subramanian@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mallikarjunappa.sangannavar@intel.com \
--cc=mgross@linux.intel.com \
--cc=robh@kernel.org \
--cc=shruthi.sanil@intel.com \
--cc=srikanth.thokala@intel.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).