From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Luca Weiss <luca.weiss@fairphone.com>
Cc: linux-arm-msm@vger.kernel.org,
~postmarketos/upstreaming@lists.sr.ht,
phone-devel@vger.kernel.org, Andy Gross <agross@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@somainline.org>,
Konrad Dybcio <konrad.dybcio@somainline.org>,
linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 4/6] pinctrl: qcom: sm6350: fix order of UFS & SDC pins
Date: Mon, 21 Mar 2022 09:15:00 -0500 [thread overview]
Message-ID: <YjiIZBbPN7pAUl1q@builder.lan> (raw)
In-Reply-To: <20220321133318.99406-5-luca.weiss@fairphone.com>
On Mon 21 Mar 08:33 CDT 2022, Luca Weiss wrote:
> In other places the SDC and UFS pins have been swapped but this was
> missed in the PINCTRL_PIN definitions. Fix that.
>
> Fixes: 7d74b55afd27 ("pinctrl: qcom: Add SM6350 pinctrl driver")
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Your proposed change looks good, but when I look at 7d74b55afd27 it
already has these entries in the correct order.
Can you please confirm that this is still applicable. Or help me see
what I am missing.
Regards,
Bjorn
> ---
> Changes in v2:
> - nothing
>
> drivers/pinctrl/qcom/pinctrl-sm6350.c | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/pinctrl/qcom/pinctrl-sm6350.c b/drivers/pinctrl/qcom/pinctrl-sm6350.c
> index 4d37b817b232..a91a86628f2f 100644
> --- a/drivers/pinctrl/qcom/pinctrl-sm6350.c
> +++ b/drivers/pinctrl/qcom/pinctrl-sm6350.c
> @@ -264,14 +264,14 @@ static const struct pinctrl_pin_desc sm6350_pins[] = {
> PINCTRL_PIN(153, "GPIO_153"),
> PINCTRL_PIN(154, "GPIO_154"),
> PINCTRL_PIN(155, "GPIO_155"),
> - PINCTRL_PIN(156, "SDC1_RCLK"),
> - PINCTRL_PIN(157, "SDC1_CLK"),
> - PINCTRL_PIN(158, "SDC1_CMD"),
> - PINCTRL_PIN(159, "SDC1_DATA"),
> - PINCTRL_PIN(160, "SDC2_CLK"),
> - PINCTRL_PIN(161, "SDC2_CMD"),
> - PINCTRL_PIN(162, "SDC2_DATA"),
> - PINCTRL_PIN(163, "UFS_RESET"),
> + PINCTRL_PIN(156, "UFS_RESET"),
> + PINCTRL_PIN(157, "SDC1_RCLK"),
> + PINCTRL_PIN(158, "SDC1_CLK"),
> + PINCTRL_PIN(159, "SDC1_CMD"),
> + PINCTRL_PIN(160, "SDC1_DATA"),
> + PINCTRL_PIN(161, "SDC2_CLK"),
> + PINCTRL_PIN(162, "SDC2_CMD"),
> + PINCTRL_PIN(163, "SDC2_DATA"),
> };
>
> #define DECLARE_MSM_GPIO_PINS(pin) \
> --
> 2.35.1
>
next prev parent reply other threads:[~2022-03-21 14:23 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-21 13:33 [PATCH v2 0/6] UFS support on SM6350 & FP4 Luca Weiss
2022-03-21 13:33 ` [PATCH v2 1/6] scsi: ufs: dt-bindings: Add SM6350 compatible string Luca Weiss
2022-03-21 13:40 ` Krzysztof Kozlowski
2022-03-21 15:41 ` Alim Akhtar
2022-03-21 21:45 ` Rob Herring
2022-03-21 21:45 ` Rob Herring
2022-03-21 13:33 ` [PATCH v2 2/6] dt-bindings: phy: qcom,qmp: Add SM6350 UFS PHY bindings Luca Weiss
2022-03-21 13:41 ` Krzysztof Kozlowski
2022-03-21 21:46 ` Rob Herring
2022-04-11 18:04 ` Vinod Koul
2022-03-21 13:33 ` [PATCH v2 3/6] phy: qcom-qmp: Add SM6350 UFS PHY support Luca Weiss
2022-04-11 18:04 ` Vinod Koul
2022-03-21 13:33 ` [PATCH v2 4/6] pinctrl: qcom: sm6350: fix order of UFS & SDC pins Luca Weiss
2022-03-21 14:15 ` Bjorn Andersson [this message]
2022-03-21 14:21 ` Luca Weiss
2022-04-17 23:42 ` Linus Walleij
2022-03-21 13:33 ` [PATCH v2 5/6] arm64: dts: qcom: sm6350: Add UFS nodes Luca Weiss
2022-03-21 13:42 ` Krzysztof Kozlowski
2022-03-21 13:33 ` [PATCH v2 6/6] arm64: dts: qcom: sm7225-fairphone-fp4: Enable UFS Luca Weiss
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