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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id w36-20020a05687033a400b000d75f1d9b82sm1768369oae.47.2022.03.24.13.47.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Mar 2022 13:47:24 -0700 (PDT) Received: (nullmailer pid 2546966 invoked by uid 1000); Thu, 24 Mar 2022 20:47:23 -0000 Date: Thu, 24 Mar 2022 15:47:23 -0500 From: Rob Herring To: Pali =?iso-8859-1?Q?Roh=E1r?= Cc: Lorenzo Pieralisi , Bjorn Helgaas , Andrew Lunn , Thomas Petazzoni , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Marek =?iso-8859-1?Q?Beh=FAn?= , Russell King , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 2/4] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property Message-ID: References: <20220302145733.12606-1-pali@kernel.org> <20220302145733.12606-3-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220302145733.12606-3-pali@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Mar 02, 2022 at 03:57:31PM +0100, Pali Rohár wrote: > This property specifies slot power limit in mW unit. It is a form-factor > and board specific value and must be initialized by hardware. > > Some PCIe controllers delegate this work to software to allow hardware > flexibility and therefore this property basically specifies what should > host bridge program into PCIe Slot Capabilities registers. > > The property needs to be specified in mW unit instead of the special format > defined by Slot Capabilities (which encodes scaling factor or different > unit). Host drivers should convert the value from mW to needed format. > > Signed-off-by: Pali Rohár > Signed-off-by: Marek Behún > > --- > This change was already accepted into dt-schema repo by Rob Herring: > https://github.com/devicetree-org/dt-schema/pull/66 Which is the definitive source for it. pci.txt should shrink or be removed, not added to. > --- > Documentation/devicetree/bindings/pci/pci.txt | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt > index 6a8f2874a24d..b0cc133ed00d 100644 > --- a/Documentation/devicetree/bindings/pci/pci.txt > +++ b/Documentation/devicetree/bindings/pci/pci.txt > @@ -32,6 +32,12 @@ driver implementation may support the following properties: > root port to downstream device and host bridge drivers can do programming > which depends on CLKREQ signal existence. For example, programming root port > not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal. > +- slot-power-limit-milliwatt: > + If present, this property specifies slot power limit in milliwatts. Host > + drivers can parse this property and use it for programming Root Port or host > + bridge, or for composing and sending PCIe Set_Slot_Power_Limit messages > + through the Root Port or host bridge when transitioning PCIe link from a > + non-DL_Up Status to a DL_Up Status. > > PCI-PCI Bridge properties > ------------------------- > -- > 2.20.1 >