From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,
Andy Shevchenko <andy@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>
Subject: Re: [PATCH v1 1/1] pinctrl: alderlake: Fix register offsets for ADL-N variant
Date: Wed, 6 Apr 2022 15:43:09 +0300 [thread overview]
Message-ID: <Yk2K3T0dLrBWgjPS@smile.fi.intel.com> (raw)
In-Reply-To: <Yk0gnG+oqpARzC+m@lahna>
On Wed, Apr 06, 2022 at 08:09:48AM +0300, Mika Westerberg wrote:
> On Tue, Apr 05, 2022 at 08:02:51PM +0300, Andy Shevchenko wrote:
> > It appears that almost traditionally the N variants have deviations
> > in the register offsets in comparison to S one. This is the case
> > for Intel Alder Lake as well. Fix register offsets for ADL-N variant.
> >
> > Fixes: 114b610b9048 ("pinctrl: alderlake: Add Intel Alder Lake-N pin controller support")
> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>
> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Pushed for fixes, thanks!
--
With Best Regards,
Andy Shevchenko
prev parent reply other threads:[~2022-04-06 15:28 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-05 17:02 [PATCH v1 1/1] pinctrl: alderlake: Fix register offsets for ADL-N variant Andy Shevchenko
2022-04-06 5:09 ` Mika Westerberg
2022-04-06 12:43 ` Andy Shevchenko [this message]
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