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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id q6-20020a056870028600b000d9be0ee766sm5076841oaf.57.2022.04.19.07.20.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Apr 2022 07:20:03 -0700 (PDT) Received: (nullmailer pid 2490554 invoked by uid 1000); Tue, 19 Apr 2022 14:20:02 -0000 Date: Tue, 19 Apr 2022 09:20:02 -0500 From: Rob Herring To: Aradhya Bhatia Cc: Jyri Sarha , Tomi Valkeinen , Vignesh Raghavendra , Nishanth Menon , DRI Development , Devicetree , Linux ARM Kernel , Linux Kernel , Nikhil Devshatwar Subject: Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt Message-ID: References: <20220419070302.16502-1-a-bhatia1@ti.com> <20220419070302.16502-2-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220419070302.16502-2-a-bhatia1@ti.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 19, 2022 at 12:33:01PM +0530, Aradhya Bhatia wrote: > The DSS IP on the ti-am65x soc supports an additional register space, > named "common1". Further. the IP services a maximum number of 2 > interrupts. > > Add the missing register space "common1" and the additional interrupt. > > Signed-off-by: Aradhya Bhatia > --- > .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++--- > 1 file changed, 7 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > index 5c7d2cbc4aac..102059e9e0d5 100644 > --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > @@ -26,6 +26,7 @@ properties: > Addresses to each DSS memory region described in the SoC's TRM. > items: > - description: common DSS register area > + - description: common1 DSS register area You've just broken the ABI. New entries have to go on the end. > - description: VIDL1 light video plane > - description: VID video plane > - description: OVR1 overlay manager for vp1 > @@ -36,6 +37,7 @@ properties: > reg-names: > items: > - const: common > + - const: common1 > - const: vidl1 > - const: vid > - const: ovr1 > @@ -64,7 +66,7 @@ properties: > maxItems: 3 > > interrupts: > - maxItems: 1 > + maxItems: 2 Once there is more than 1, we need to know what each entry is and the order. > > power-domains: > maxItems: 1 > @@ -122,13 +124,14 @@ examples: > dss: dss@4a00000 { > compatible = "ti,am65x-dss"; > reg = <0x04a00000 0x1000>, /* common */ > + reg = <0x04a01000 0x1000>, /* common1 */ > <0x04a02000 0x1000>, /* vidl1 */ > <0x04a06000 0x1000>, /* vid */ > <0x04a07000 0x1000>, /* ovr1 */ > <0x04a08000 0x1000>, /* ovr2 */ > <0x04a0a000 0x1000>, /* vp1 */ > <0x04a0b000 0x1000>; /* vp2 */ > - reg-names = "common", "vidl1", "vid", > + reg-names = "common", "common1". "vidl1", "vid", > "ovr1", "ovr2", "vp1", "vp2"; > ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; > power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; > @@ -136,7 +139,8 @@ examples: > <&k3_clks 216 1>, > <&k3_clks 67 2>; > clock-names = "fck", "vp1", "vp2"; > - interrupts = ; > + interrupts = , > + ; > ports { > #address-cells = <1>; > #size-cells = <0>; > -- > 2.35.3 > >