From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30CB6C433EF for ; Wed, 13 Apr 2022 21:21:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238975AbiDMVX7 (ORCPT ); Wed, 13 Apr 2022 17:23:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239274AbiDMVXD (ORCPT ); Wed, 13 Apr 2022 17:23:03 -0400 Received: from mail-oi1-f181.google.com (mail-oi1-f181.google.com [209.85.167.181]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DE9A2BB37; Wed, 13 Apr 2022 14:20:41 -0700 (PDT) Received: by mail-oi1-f181.google.com with SMTP id q129so3431701oif.4; Wed, 13 Apr 2022 14:20:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=BNnhzbT7x5Fwfm2D+LNQD+lbH1XqfFIidCgzY9zOuGk=; b=FIY+MZHCG+BzxvP7M0SwV6pj/njJoYdDjJcTFRGITCWMOVGTsxJpB3dwFbowihllgH 51rAOpR1q1mVLcc26h7v7TUcIYjy2nedRK3T0x9BXE0gp9BPEOVzI5gwgf56LjjuxULK dvzNjEwAkdKoLb26IPrZPYZkxMve48vSPABtAFkrwgpmfNhexH6uryguDUAFsx/dxQJK d/gjYyaMXI8jbHsOuO6IN9UOOAxtcTd9M3ITLWTHcqIvDBJyrqwfPPo+Q3HVMTAHq12w /SdlAbi1BTKoSvsSXSB6Ds+Ix70S+q/jWT1dN1dcRxiSwIJap3pdDQaM1zfYkE/rOLw3 BUJA== X-Gm-Message-State: AOAM530/rgC7sAChBqqgZNYtMQ9QjSmTzJOiUAzwCR7CJJrl2ob5wuEb eyYmgZSKKx31B3OMAtAlfwY4napT8w== X-Google-Smtp-Source: ABdhPJzOAUPoYvywkyjx8QaQOVnaIDTerWLm9Yg9DWHDGQeYUOO9E66kaHrhsX05kwA+rd6RTOa7QQ== X-Received: by 2002:a05:6808:118f:b0:2d4:13f1:8504 with SMTP id j15-20020a056808118f00b002d413f18504mr332417oil.90.1649884840198; Wed, 13 Apr 2022 14:20:40 -0700 (PDT) Received: from robh.at.kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id bx16-20020a0568081b1000b002f7966564b4sm59862oib.43.2022.04.13.14.20.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Apr 2022 14:20:39 -0700 (PDT) Received: (nullmailer pid 3947483 invoked by uid 1000); Wed, 13 Apr 2022 21:20:38 -0000 Date: Wed, 13 Apr 2022 16:20:38 -0500 From: Rob Herring To: xinlei.lee@mediatek.com Cc: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, matthias.bgg@gmail.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, rex-bc.chen@mediatek.com, jitao.shi@mediatek.com, Project_Global_Chrome_Upstream_Group@mediatek.com Subject: Re: [PATCH v4,1/3] dt-bindings: display: mediatek: dsi: Convert dsi_dtbinding to .yaml Message-ID: References: <1649495514-25746-1-git-send-email-xinlei.lee@mediatek.com> <1649495514-25746-2-git-send-email-xinlei.lee@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1649495514-25746-2-git-send-email-xinlei.lee@mediatek.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Apr 09, 2022 at 05:11:52PM +0800, xinlei.lee@mediatek.com wrote: > From: Xinlei Lee > > Convert mediatek,dsi.txt to mediatek,dsi.yaml format > > Signed-off-by: Xinlei Lee > --- > .../display/mediatek/mediatek,dsi.txt | 62 --------- > .../display/mediatek/mediatek,dsi.yaml | 118 ++++++++++++++++++ > 2 files changed, 118 insertions(+), 62 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml > new file mode 100644 > index 000000000000..431bb981394f > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml > @@ -0,0 +1,118 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek DSI Controller Device Tree Bindings > + > +maintainers: > + - CK Hu > + - Jitao Shi > + - Xinlei Lee > + > +description: | > + The MediaTek DSI function block is a sink of the display subsystem and can > + drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- > + channel output. allOf: - $ref: /schemas/display/dsi-controller.yaml# > + > +properties: > + compatible: > + enum: > + - mediatek,mt2701-dsi > + - mediatek,mt7623-dsi > + - mediatek,mt8167-dsi > + - mediatek,mt8173-dsi > + - mediatek,mt8183-dsi > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + clocks: > + items: > + - description: Engine Clock > + - description: Digital Clock > + - description: HS Clock > + > + clock-names: > + items: > + - const: engine > + - const: digital > + - const: hs > + > + resets: > + maxItems: 1 > + > + phys: > + maxItems: 1 > + > + phy-names: > + items: > + - const: dphy > + > + port: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output port node. This port should be connected to the input > + port of an attached DSI panel or DSI-to-eDP encoder chip. > + > + > + "#address-cells": > + const: 2 > + > + "#size-cells": > + const: 2 > + > +required: > + - compatible > + - reg > + - interrupts > + - power-domains > + - clocks > + - clock-names > + - phys > + - phy-names > + - port > + > +additionalProperties: false with the above, unevaluatedProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + #include > + #include > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + dsi0: dsi@14014000 { > + compatible = "mediatek,mt8183-dsi"; > + reg = <0 0x14014000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DSI0_MM>, > + <&mmsys CLK_MM_DSI0_IF>, > + <&mipi_tx0>; > + clock-names = "engine", "digital", "hs"; > + resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>; > + phys = <&mipi_tx0>; > + phy-names = "dphy"; > + port { > + dsi0_out: endpoint { > + remote-endpoint = <&panel_in>; > + }; > + }; > + }; > + }; > + > +... > -- > 2.18.0 > >