From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 416FAC433FE for ; Thu, 21 Apr 2022 14:44:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1389588AbiDUOrO (ORCPT ); Thu, 21 Apr 2022 10:47:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52166 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1389579AbiDUOrH (ORCPT ); Thu, 21 Apr 2022 10:47:07 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A27341F8B for ; Thu, 21 Apr 2022 07:44:17 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 46157B825B6 for ; Thu, 21 Apr 2022 14:44:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7EB93C385A5; Thu, 21 Apr 2022 14:44:12 +0000 (UTC) Date: Thu, 21 Apr 2022 15:44:08 +0100 From: Catalin Marinas To: Arnd Bergmann Cc: Christoph Hellwig , Ard Biesheuvel , Herbert Xu , Will Deacon , Marc Zyngier , Greg Kroah-Hartman , Andrew Morton , Linus Torvalds , Linux Memory Management List , Linux ARM , Linux Kernel Mailing List , "David S. Miller" Subject: Re: [PATCH 07/10] crypto: Use ARCH_DMA_MINALIGN instead of ARCH_KMALLOC_MINALIGN Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Apr 21, 2022 at 03:47:30PM +0200, Arnd Bergmann wrote: > On Thu, Apr 21, 2022 at 3:25 PM Catalin Marinas wrote: > > On Thu, Apr 21, 2022 at 02:28:45PM +0200, Arnd Bergmann wrote: > > > We also know that larger slabs are all cacheline aligned, so simply > > > comparing the transfer size is enough to rule out most, in this case > > > any transfer larger than 96 bytes must come from the kmalloc-128 > > > or larger cache, so that works like before. > > > > There's also the case with 128-byte cache lines and kmalloc-192. > > Sure, but that's much less common, as the few machines with 128 byte > cache lines tend to also have cache coherent devices IIRC, so we'd > skip the bounce buffer entirely. Do you know which machines still have 128-byte cache lines _and_ non-coherent DMA? If there isn't any that matters, I'd reduce ARCH_DMA_MINALIGN to 64 now (while trying to get to even smaller kmalloc caches). > > > For transfers <=96 bytes, the possibilities are: > > > > > > 1.kmalloc-32 or smaller, always needs to bounce > > > 2. kmalloc-96, but at least one byte in partial cache line, > > > need to bounce > > > 3. kmalloc-64, may skip the bounce. > > > 4. kmalloc-128 or larger, or not a slab cache but a partial > > > transfer, may skip the bounce. > > > > > > I would guess that the first case is the most common here, > > > so unless bouncing one or two cache lines is extremely > > > expensive, I don't expect it to be worth optimizing for the latter > > > two cases. > > > > I think so. If someone complains of a performance regression, we can > > look at optimising the bounce. I have a suspicion the cost of copying > > two cache lines is small compared to swiotlb_find_slots() etc. > > That is possible, and we'd definitely have to watch out for > performance regressions, I'm just skeptical that the cases that > suffer from the extra bouncer buffering on 33..64 byte allocations > benefit much from having a special case if the 1...32 and 65..96 > byte allocations are still slow. > > Another simpler way to do this might be to just not create the > kmalloc-96 (or kmalloc-192) caches, and assuming that any > transfer >=33 (or 65) bytes is safe. I'll give the dma bounce idea a go next week, see how it looks. -- Catalin